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| author | Alex Bee <knaerzche@gmail.com> | 2021-05-27 17:44:54 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2021-06-22 00:21:27 +0200 |
| commit | db3fc8fa0fcfa481cd8087c2ee068d1d1988c3a2 (patch) | |
| tree | 3b922977c36bce0cf39f48667b53b08ae5fd6a44 | |
| parent | 9d34d4aa896d00d398d799caa839a1494ba7c018 (diff) | |
| download | linux-db3fc8fa0fcfa481cd8087c2ee068d1d1988c3a2.tar.gz | |
ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188
Add the vpu node to the common rk3xxx.dtsi and only the powerdomain
property to the SoC specific device trees.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210527154455.358869-12-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm/boot/dts/rk3066a.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/rk3188.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/rk3xxx.dtsi | 12 |
3 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b15cbbe23ffc..f5a665b5d209 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -868,6 +868,10 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + power-domains = <&power RK3066_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index b36fcdd9a516..793a1b9117fe 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -801,6 +801,11 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; + power-domains = <&power RK3188_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index f9bbc2424444..616a828e0c6e 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -47,6 +47,18 @@ status = "disabled"; }; + vpu: video-codec@10104000 { + compatible = "rockchip,rk3066-vpu"; + reg = <0x10104000 0x800>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + }; + L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; |