diff options
| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2020-12-18 16:07:18 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2020-12-22 17:54:54 +0200 |
| commit | 4f3dd47acbed7dd50f9add02b204db14e4af967f (patch) | |
| tree | 69a1a350191288b7020c74c8a9e8aca9a5f5b1b0 | |
| parent | ced42f2df5fd8621c896faeafe7ecc0ea8b2ea81 (diff) | |
| download | linux-4f3dd47acbed7dd50f9add02b204db14e4af967f.tar.gz | |
drm/i915: Check for FRL training before DP Link training
This patch calls functions to check FRL training requirements
for an HDMI2.1 sink, when connected through PCON.
The call is made before the DP link training. In case FRL is not
required or failure during FRL training, the TMDS mode is selected
for the pcon.
v2: moved check_frl_training() just after FEC READY, before
starting DP link training.
v3: rebase
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201218103723.30844-11-ankit.k.nautiyal@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 92940a0c5ef8..fd39d3966914 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3651,6 +3651,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_dp_sink_set_fec_ready(intel_dp, crtc_state); + intel_dp_check_frl_training(intel_dp); + /* * 7.i Follow DisplayPort specification training sequence (see notes for * failure handling) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 26f82e38ed05..b8dc247dfd71 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4252,6 +4252,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp); + intel_dp_check_frl_training(intel_dp); intel_dp_start_link_train(intel_dp, pipe_config); intel_dp_stop_link_train(intel_dp, pipe_config); @@ -6173,6 +6174,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, !intel_dp_mst_is_master_trans(crtc_state)) continue; + intel_dp_check_frl_training(intel_dp); intel_dp_start_link_train(intel_dp, crtc_state); intel_dp_stop_link_train(intel_dp, crtc_state); break; |