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author | Jani Nikula <jani.nikula@intel.com> | 2022-04-11 16:01:56 +0300 |
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committer | Jani Nikula <jani.nikula@intel.com> | 2022-04-11 16:01:56 +0300 |
commit | 83970cd63b9f864525761137b500113ab0b49c94 (patch) | |
tree | 747b97113d60666cbb44f8a5633b961b7eda3c86 /Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml | |
parent | 618f5df1f6a5a3f29fad824116da291a7d14ab5e (diff) | |
parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) | |
download | linux-83970cd63b9f864525761137b500113ab0b49c94.tar.gz |
Merge drm/drm-next into drm-intel-next
Sync up with v5.18-rc1, in particular to get 5e3094cfd9fb
("drm/i915/xehpsdv: Add has_flat_ccs to device info").
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml | 129 |
1 files changed, 129 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml new file mode 100644 index 000000000000..22b91a27d776 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/samsung,exynos-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC USB 3.0 DWC3 Controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + enum: + - samsung,exynos5250-dwusb3 + - samsung,exynos5433-dwusb3 + - samsung,exynos7-dwusb3 + + '#address-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + ranges: true + + '#size-cells': + const: 1 + + vdd10-supply: + description: 1.0V power supply + + vdd33-supply: + description: 3.0V/3.3V power supply + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml# + description: Required child node + +required: + - compatible + - '#address-cells' + - clocks + - clock-names + - ranges + - '#size-cells' + - vdd10-supply + - vdd33-supply + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos5250-dwusb3 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: usbdrd30 + + - if: + properties: + compatible: + contains: + const: samsung,exynos54333-dwusb3 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: aclk + - const: susp_clk + - const: pipe_pclk + - const: phyclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-dwusb3 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: usbdrd30 + - const: usbdrd30_susp_clk + - const: usbdrd30_axius_clk + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5420.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb { + compatible = "samsung,exynos5250-dwusb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; + + usb@12000000 { + compatible = "snps,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; + }; + }; |