diff options
| author | Amit Nischal <anischal@codeaurora.org> | 2018-11-25 10:06:07 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-11-27 16:24:44 -0800 |
| commit | e431c92188a9b76c16707302a9fe848a70982c13 (patch) | |
| tree | 1ced6bb9add815b7e5bebe95c9d269fd2d79a89b /Documentation | |
| parent | 651022382c7f8da46cb4872a545ee1da6d097d2a (diff) | |
| download | linux-e431c92188a9b76c16707302a9fe848a70982c13.tar.gz | |
dt-bindings: clock: Introduce QCOM Graphics clock bindings
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Add input clocks property]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,gpucc.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt new file mode 100644 index 000000000000..9d0358cc08b4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -0,0 +1,22 @@ +Qualcomm Graphics Clock & Reset Controller Binding +-------------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-gpucc" +- reg : shall contain base register location and length +- #clock-cells : from common clock binding, shall contain 1 +- #reset-cells : from common reset binding, shall contain 1 +- #power-domain-cells : from generic power domain binding, shall contain 1 +- clocks : shall contain the XO clock +- clock-names : shall be "xo" + +Example: + gpucc: clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0x5090000 0x9000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; |