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author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2017-10-11 15:39:38 +0200 |
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committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2017-10-11 15:39:38 +0200 |
commit | 8af4b3d7044d83c5426da6e45a9c7948bc7fa231 (patch) | |
tree | 76e15a6cea6b526fe30c679f6e9bf60b08acf983 /arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | |
parent | a5950f2617f71a3dce16520c4907bcdb31e654ba (diff) | |
parent | c2ebf788f927dcca72beead19fab5f5aba79a098 (diff) | |
download | linux-8af4b3d7044d83c5426da6e45a9c7948bc7fa231.tar.gz |
Merge branch 'acpi-pm' into pm-sleep
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-gxl.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index d6876e64979e..d8dd3298b15c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -281,6 +281,17 @@ }; }; + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "BOOT_8"; + bias-pull-down; + }; + }; + nor_pins: nor { mux { groups = "nor_d", @@ -319,6 +330,17 @@ }; }; + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "CARD_2"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "CARD_2"; + bias-pull-down; + }; + }; + sdio_pins: sdio { mux { groups = "sdio_d0", @@ -331,6 +353,17 @@ }; }; + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "GPIOX_4"; + bias-pull-down; + }; + }; + sdio_irq_pins: sdio_irq { mux { groups = "sdio_irq"; @@ -603,21 +636,21 @@ &sd_emmc_a { clocks = <&clkc CLKID_SD_EMMC_A>, - <&xtal>, + <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, - <&xtal>, + <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_c { clocks = <&clkc CLKID_SD_EMMC_C>, - <&xtal>, + <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; |