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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 16:36:14 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 16:36:14 +0800 |
| commit | d279134168c78ac2caa1f7cd2a846579da1c93ac (patch) | |
| tree | d77ab5ef3f2ac782823aea728906a7942af1c35a /arch/loongarch/include/asm/pgtable-bits.h | |
| parent | 235d074fdc9a69e3720b8bb6efeb7c6d30c12d8e (diff) | |
| download | linux-d279134168c78ac2caa1f7cd2a846579da1c93ac.tar.gz | |
LoongArch: Use TLB for ioremap()
We can support more cache attributes (e.g., CC, SUC and WUC) and page
protection when we use TLB for ioremap(). The implementation is based
on GENERIC_IOREMAP.
The existing simple ioremap() implementation has better performance so
we keep it and introduce ARCH_IOREMAP to control the selection.
We move pagetable_init() earlier to make early ioremap() works, and we
modify the PCI ecam mapping because the TLB-based version of ioremap()
will actually take the size into account.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/pgtable-bits.h')
| -rw-r--r-- | arch/loongarch/include/asm/pgtable-bits.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/pgtable-bits.h b/arch/loongarch/include/asm/pgtable-bits.h index 9ca147a29bab..3d1e0a69975a 100644 --- a/arch/loongarch/include/asm/pgtable-bits.h +++ b/arch/loongarch/include/asm/pgtable-bits.h @@ -83,8 +83,11 @@ _PAGE_GLOBAL | _PAGE_KERN | _CACHE_SUC) #define PAGE_KERNEL_WUC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _PAGE_KERN | _CACHE_WUC) + #ifndef __ASSEMBLY__ +#define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_SUC) + #define pgprot_noncached pgprot_noncached static inline pgprot_t pgprot_noncached(pgprot_t _prot) |