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| author | Nicholas Piggin <npiggin@gmail.com> | 2021-05-28 19:07:41 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-06-10 22:12:14 +1000 |
| commit | 2e1ae9cd56f8616a707185f3c6cb7ee2a20809e1 (patch) | |
| tree | 820ef3667a86af583ace51c09976380cf92dd23f /arch/powerpc/mm/mmu_context.c | |
| parent | 41f779917669fcc28a7f5646d1f7a85043c9d152 (diff) | |
| download | linux-2e1ae9cd56f8616a707185f3c6cb7ee2a20809e1.tar.gz | |
KVM: PPC: Book3S HV: Implement radix prefetch workaround by disabling MMU
Rather than partition the guest PID space + flush a rogue guest PID to
work around this problem, instead fix it by always disabling the MMU when
switching in or out of guest MMU context in HV mode.
This may be a bit less efficient, but it is a lot less complicated and
allows the P9 path to trivally implement the workaround too. Newer CPUs
are not subject to this issue.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210528090752.3542186-22-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/mm/mmu_context.c')
| -rw-r--r-- | arch/powerpc/mm/mmu_context.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/powerpc/mm/mmu_context.c b/arch/powerpc/mm/mmu_context.c index a857af401738..74246536b832 100644 --- a/arch/powerpc/mm/mmu_context.c +++ b/arch/powerpc/mm/mmu_context.c @@ -83,9 +83,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, if (cpu_has_feature(CPU_FTR_ALTIVEC)) asm volatile ("dssall"); - if (new_on_cpu) - radix_kvm_prefetch_workaround(next); - else + if (!new_on_cpu) membarrier_arch_switch_mm(prev, next, tsk); /* |