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| author | Steven Whitehouse <swhiteho@redhat.com> | 2006-05-12 10:48:52 -0400 |
|---|---|---|
| committer | Steven Whitehouse <swhiteho@redhat.com> | 2006-05-12 10:48:52 -0400 |
| commit | 7d63b54a65ce902f9aaa8efe8192aa3b983264d4 (patch) | |
| tree | 250a77bebe92cbd6edac70a649866044295876db /arch/ppc/kernel/head_8xx.S | |
| parent | fd88de569b802c4a04aaa6ee74667775f4aed8c6 (diff) | |
| parent | d8c3291c73b958243b33f8509d4507e76dafd055 (diff) | |
| download | linux-7d63b54a65ce902f9aaa8efe8192aa3b983264d4.tar.gz | |
Merge branch 'master'
Diffstat (limited to 'arch/ppc/kernel/head_8xx.S')
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ec53c7d65f2b..7a2f20583be4 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -355,9 +355,7 @@ InstructionTLBMiss: . = 0x1200 DataStoreTLBMiss: -#ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) -#endif DO_8xx_CPU6(0x3f80, r3) mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mfcr r10 @@ -417,9 +415,7 @@ DataStoreTLBMiss: lwz r11, 0(r0) mtcr r11 lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is an instruction TLB error on the MPC8xx. This could be due |