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| author | Zong Li <zong.li@sifive.com> | 2019-10-28 00:42:47 -0700 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-11-12 12:04:52 -0800 |
| commit | 6b57ba8ed48a3ee3d6b53294ccbf02b8cb83c604 (patch) | |
| tree | bc86c2336402e4a3a3af3faa9945bb751e6ba5ac /arch/riscv/include/asm/hwcap.h | |
| parent | 0fdc636cd95ceeba48b8c171ac338df46b795101 (diff) | |
| download | linux-6b57ba8ed48a3ee3d6b53294ccbf02b8cb83c604.tar.gz | |
riscv: clean up the macro format in each header file
There are many different formats in each header now, such as
_ASM_XXX_H, __ASM_XXX_H, _ASM_RISCV_XXX_H, RISCV_XXX_H, etc., This patch
tries to unify the format by using _ASM_RISCV_XXX_H, because the most
header use it now. This patch also adds the conditional to the headers
if they lost it.
Signed-off-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/include/asm/hwcap.h')
| -rw-r--r-- | arch/riscv/include/asm/hwcap.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ecb7c6a57b1..1bb0cd04aec3 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -5,8 +5,8 @@ * Copyright (C) 2012 ARM Ltd. * Copyright (C) 2017 SiFive */ -#ifndef __ASM_HWCAP_H -#define __ASM_HWCAP_H +#ifndef _ASM_RISCV_HWCAP_H +#define _ASM_RISCV_HWCAP_H #include <uapi/asm/hwcap.h> @@ -23,4 +23,5 @@ enum { extern unsigned long elf_hwcap; #endif -#endif + +#endif /* _ASM_RISCV_HWCAP_H */ |