diff options
| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-19 21:14:56 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-19 21:15:36 -0700 |
| commit | 8916c9054f940acbd735e33067e8a7e5a06f8834 (patch) | |
| tree | bcdff33373241d7f870e79917c4421969902ded5 /arch/riscv/kernel/cpufeature.c | |
| parent | b49816611eaceb66a00c8b18e6d7bcee63eba86b (diff) | |
| parent | 171549f829dfebf1f44ffa76d3191bdc032d4cdb (diff) | |
| download | linux-8916c9054f940acbd735e33067e8a7e5a06f8834.tar.gz | |
RISC-V: Support for 64bit hartid on RV64 platforms
The hartid can be a 64bit value on RV64 platforms. This series updates
the code so that 64bit hartid can be supported on RV64 platforms.
* 'riscv-64bit_hartid' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git:
riscv/efi_stub: Add 64bit boot-hartid support on RV64
riscv: cpu: Add 64bit hartid support on RV64
riscv: smp: Add 64bit hartid support on RV64
riscv: spinwait: Fix hartid variable type
riscv: cpu_ops_sbi: Add 64bit hartid support on RV64
Diffstat (limited to 'arch/riscv/kernel/cpufeature.c')
| -rw-r--r-- | arch/riscv/kernel/cpufeature.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b3ec44e25f5..e233fe154c96 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -72,8 +72,9 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; + int i, j, rc; static unsigned long isa2hwcap[256] = {0}; + unsigned long hartid; isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; @@ -91,7 +92,8 @@ void __init riscv_fill_hwcap(void) DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - if (riscv_of_processor_hartid(node) < 0) + rc = riscv_of_processor_hartid(node, &hartid); + if (rc < 0) continue; if (of_property_read_string(node, "riscv,isa", &isa)) { |