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| author | Yash Shah <yash.shah@sifive.com> | 2020-01-03 09:43:20 +0530 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2020-01-03 00:56:23 -0800 |
| commit | cfda8617e22a8bf217a613d0b3ba3a38778443ba (patch) | |
| tree | 85fbdb2001a712861d788616d17dc654e28740dd /arch/riscv/kernel/ftrace.c | |
| parent | 0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fe (diff) | |
| download | linux-cfda8617e22a8bf217a613d0b3ba3a38778443ba.tar.gz | |
riscv: dts: Add DT support for SiFive L2 cache controller
Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/ftrace.c')
0 files changed, 0 insertions, 0 deletions