diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2019-03-07 15:14:55 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-04-01 10:45:11 +0200 |
| commit | 34775209ba37bff3b4e60ddee0a2d69966146a5d (patch) | |
| tree | 56e95653b6f0ae3dfc4da6b7cc362d450e52470a /drivers/clk/meson/g12a.h | |
| parent | 39b8500283b45252e2f9ad9d60992f2c0d3a1659 (diff) | |
| download | linux-34775209ba37bff3b4e60ddee0a2d69966146a5d.tar.gz | |
clk: meson-g12a: add PCIE PLL clocks
Add the PCIe reference clock feeding the USB3 + PCIE combo PHY.
This PLL needs a very precise register sequence to permit to be locked,
thus using the specific clk-pll pcie ops.
The PLL is then followed by :
- a fixed /2 divider
- a 5-bit 1-based divider
- a final /2 divider
This reference clock is fixed to 100MHz, thus only a single PLL setup
is added.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-4-narmstrong@baylibre.com
Diffstat (limited to 'drivers/clk/meson/g12a.h')
| -rw-r--r-- | drivers/clk/meson/g12a.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 70aa469ca1cf..1393a09730a6 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -186,8 +186,11 @@ #define CLKID_CPU_CLK_AXI 195 #define CLKID_CPU_CLK_TRACE_DIV 196 #define CLKID_CPU_CLK_TRACE 197 +#define CLKID_PCIE_PLL_DCO 198 +#define CLKID_PCIE_PLL_DCO_DIV2 199 +#define CLKID_PCIE_PLL_OD 200 -#define NR_CLKS 198 +#define NR_CLKS 202 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/g12a-clkc.h> |