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| author | Feifei Xu <Feifei.Xu@amd.com> | 2020-11-19 18:12:26 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 22:54:49 -0400 |
| commit | 5c03e5843e6bd1e6f2271a54c9b30524ba78bb8f (patch) | |
| tree | b82f270e2f490bdcc81dc3d98e146c13911dccb0 /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | 4c2e5f513e950038c594df04ae2cc511fa854ccb (diff) | |
| download | linux-5c03e5843e6bd1e6f2271a54c9b30524ba78bb8f.tar.gz | |
drm/amdgpu:add smu mode1/2 support for aldebaran
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 56 |
1 files changed, 19 insertions, 37 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f8fbf6aa1a44..8298c608f181 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -650,40 +650,6 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, } -static int soc15_asic_mode1_reset(struct amdgpu_device *adev) -{ - u32 i; - int ret = 0; - - amdgpu_atombios_scratch_regs_engine_hung(adev, true); - - dev_info(adev->dev, "GPU mode1 reset\n"); - - /* disable BM */ - pci_clear_master(adev->pdev); - - amdgpu_device_cache_pci_state(adev->pdev); - - ret = psp_gpu_reset(adev); - if (ret) - dev_err(adev->dev, "GPU mode1 reset failed\n"); - - amdgpu_device_load_pci_state(adev->pdev); - - /* wait for asic to come out of reset */ - for (i = 0; i < adev->usec_timeout; i++) { - u32 memsize = adev->nbio.funcs->get_memsize(adev); - - if (memsize != 0xffffffff) - break; - udelay(1); - } - - amdgpu_atombios_scratch_regs_engine_hung(adev, false); - - return ret; -} - static int soc15_asic_baco_reset(struct amdgpu_device *adev) { struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); @@ -708,13 +674,21 @@ static enum amd_reset_method soc15_asic_reset_method(struct amdgpu_device *adev) { bool baco_reset = false; + bool connected_to_cpu = false; struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) + connected_to_cpu = true; + if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || amdgpu_reset_method == AMD_RESET_METHOD_BACO || - amdgpu_reset_method == AMD_RESET_METHOD_PCI) - return amdgpu_reset_method; + amdgpu_reset_method == AMD_RESET_METHOD_PCI) { + /* If connected to cpu, driver only support mode2 */ + if (connected_to_cpu) + return AMD_RESET_METHOD_MODE2; + return amdgpu_reset_method; + } if (amdgpu_reset_method != -1) dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", @@ -740,6 +714,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev) if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) baco_reset = false; break; + case CHIP_ALDEBARAN: + /* + * 1.connected to cpu: driver issue mode2 reset + * 2.discret gpu: driver issue mode1 reset + */ + if (connected_to_cpu) + return AMD_RESET_METHOD_MODE2; + break; default: break; } @@ -769,7 +751,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev) return amdgpu_dpm_mode2_reset(adev); default: dev_info(adev->dev, "MODE1 reset\n"); - return soc15_asic_mode1_reset(adev); + return amdgpu_device_mode1_reset(adev); } } |