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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-23 18:30:05 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-26 10:24:50 +0200 |
| commit | b8fc2f6a18052194c486b407765a4f5e4dca692d (patch) | |
| tree | 1a1db94b0ffb90cd25d65ae8e419acbd6673e8c7 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | e6f0bfc4fb963da9e945ebc6330db9a4d756ba78 (diff) | |
| download | linux-b8fc2f6a18052194c486b407765a4f5e4dca692d.tar.gz | |
drm/i915: set the correct eDP aux channel clock divider on DDI
The cdclk frequency is not always the same, so the value here should
be adjusted to match it.
Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 7ea373ffe7a1..8d49a964cb2c 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1239,7 +1239,7 @@ void intel_disable_ddi(struct intel_encoder *encoder) /* This will be needed in the future, so leave it here for now */ } -static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) +int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) { if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) return 450; |