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| author | Arnd Bergmann <arnd@arndb.de> | 2012-03-06 16:12:13 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-03-06 16:12:26 +0000 |
| commit | 6b60805502fecc5ce05dad68fd242c4f3a1d1f1b (patch) | |
| tree | a53537e00ede0a31b8f9f91c1d79d1e1a6670797 /drivers/gpu/drm/i915/intel_display.c | |
| parent | 4c75aab698d4b7cc08f3a5dd329fc7e9af3d0e3c (diff) | |
| parent | af829310e8a914ad17ed61a7b18b14b4f457bca1 (diff) | |
| download | linux-6b60805502fecc5ce05dad68fd242c4f3a1d1f1b.tar.gz | |
Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes
* 'fixes' of git://github.com/hzhuang1/linux: (3 commits)
ARM: pxa: fix invalid mfp pin issue
ARM: pxa: remove duplicated registeration on pxa-gpio
ARM: pxa: add dummy clock for pxa25x and pxa27x
Includes an update to v3.3-rc6
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f425b23e3803..f851db7be2cc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4680,8 +4680,17 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, crtc = intel_get_crtc_for_plane(dev, plane); clock = crtc->mode.clock; + if (!clock) { + *sprite_wm = 0; + return false; + } line_time_us = (sprite_width * 1000) / clock; + if (!line_time_us) { + *sprite_wm = 0; + return false; + } + line_count = (latency_ns / line_time_us + 1000) / 1000; line_size = sprite_width * pixel_size; @@ -6175,7 +6184,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) int i; /* The clocks have to be on to load the palette. */ - if (!crtc->enabled) + if (!crtc->enabled || !intel_crtc->active) return; /* use legacy palette for Ironlake */ @@ -6561,7 +6570,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev, mode_cmd.height = mode->vdisplay; mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); - mode_cmd.pixel_format = 0; + mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); return intel_framebuffer_create(dev, &mode_cmd, obj); } @@ -8185,7 +8194,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) if (intel_enable_rc6(dev_priv->dev)) rc6_mask = GEN6_RC_CTL_RC6_ENABLE | - (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0; + ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0); I915_WRITE(GEN6_RC_CONTROL, rc6_mask | |