diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-05-13 16:39:03 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-05-28 20:46:55 +0300 |
| commit | 638d87c4a70e497465cc489e03310de39efa0f82 (patch) | |
| tree | fab600630694a0ad8eea67664f4e7ad64cc0740e /drivers/gpu/drm/i915/intel_display.c | |
| parent | c017cf6b1a5c7a218f7171bb8061132d9a23a918 (diff) | |
| download | linux-638d87c4a70e497465cc489e03310de39efa0f82.tar.gz | |
drm/i915: Update pipe gamma enable bits when C8 planes are getting enabled/disabled
When the first C8 plane gets enabled, or the last one gets disabled we
may need to enable/disable the pipe gamma for the other active planes.
Check for that and run through the normal intel_color_check() path.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190513133904.20374-2-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0e3abc7f65e3..4cbea30439ba 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11507,6 +11507,17 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) return 0; } +static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); + struct intel_atomic_state *state = + to_intel_atomic_state(new_crtc_state->base.state); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + + return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; +} + static int intel_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { @@ -11530,6 +11541,13 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, return ret; } + /* + * May need to update pipe gamma enable bits + * when C8 planes are getting enabled/disabled. + */ + if (c8_planes_changed(pipe_config)) + crtc_state->color_mgmt_changed = true; + if (mode_changed || pipe_config->update_pipe || crtc_state->color_mgmt_changed) { ret = intel_color_check(pipe_config); |