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author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-04-27 15:44:24 +0300 |
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committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-04-29 09:58:53 +0300 |
commit | 5f68c275b46460e6c2923763e7842011dabd3585 (patch) | |
tree | c88b7a63982fe7c508276e0d1c676328c7c81e84 /drivers/gpu/drm/i915/intel_dpio_phy.c | |
parent | 6da2e61602e3511a07d19df9494b07eb1f4c0ef6 (diff) | |
download | linux-5f68c275b46460e6c2923763e7842011dabd3585.tar.gz |
drm/i915: Unduplicate pre encoder enabling phy code
The phy code in vlv_pre_enable_dp() and vlv_hdmi_pre_enable() is
exectly the same, so extract it to intel_dpio_phy.c.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-10-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpio_phy.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dpio_phy.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c index 975965a7fe73..2c14bf035a0b 100644 --- a/drivers/gpu/drm/i915/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c @@ -423,3 +423,33 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder) vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); mutex_unlock(&dev_priv->sb_lock); } + +void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + enum dpio_channel port = vlv_dport_to_channel(dport); + int pipe = intel_crtc->pipe; + u32 val; + + mutex_lock(&dev_priv->sb_lock); + + /* Enable clock channels for this port */ + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); + val = 0; + if (pipe) + val |= (1<<21); + else + val &= ~(1<<21); + val |= 0x001000c4; + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); + + /* Program lane clock */ + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); + + mutex_unlock(&dev_priv->sb_lock); +} |