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authorVille Syrjälä <ville.syrjala@linux.intel.com>2018-12-21 19:14:30 +0200
committerVille Syrjälä <ville.syrjala@linux.intel.com>2019-01-30 16:03:01 +0200
commit17b16054b1115559df126c9d7e727770194d39e3 (patch)
tree153dc9de0c230eddf170a3bc1b2681cf3397f8ae /drivers/gpu/drm/i915/intel_pm.c
parent692927f4e9058fbdae1baecf72d85659bbc3c59c (diff)
downloadlinux-17b16054b1115559df126c9d7e727770194d39e3.tar.gz
drm/i915: Fix bits vs. bytes mixup in dbuf block size computation
The spec used to say "8bpp" which someone took to mean 8 bytes per pixel when in fact it was supposed to be 8 bits per pixel. The spec has been updated to make it more clear now. Fix the code to match. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-4-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7473d6ea4bfe..59e186b30d97 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4617,7 +4617,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
intel_pstate);
if (INTEL_GEN(dev_priv) >= 11 &&
- fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
wp->dbuf_block_size = 256;
else
wp->dbuf_block_size = 512;