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| author | Imre Deak <imre.deak@intel.com> | 2016-05-03 15:54:19 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-05-03 16:49:09 +0300 |
| commit | 48e5d68d28f00c0cadac5a830980ff3222781abb (patch) | |
| tree | a8287da28da8a0674c92e5c7b6708fff953e3c8e /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 9a41e17de38e8528816598e728f784da68df17f7 (diff) | |
| download | linux-48e5d68d28f00c0cadac5a830980ff3222781abb.tar.gz | |
drm/i915/bdw: Add missing delay during L3 SQC credit programming
BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.
CC: stable@vger.kernel.org
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-2-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2422ac38ce5d..227cd2d395a9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6738,6 +6738,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev) misccpctl = I915_READ(GEN7_MISCCPCTL); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); + /* + * Wait at least 100 clocks before re-enabling clock gating. See + * the definition of L3SQCREG1 in BSpec. + */ + POSTING_READ(GEN8_L3SQCREG1); + udelay(1); I915_WRITE(GEN7_MISCCPCTL, misccpctl); /* |