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| author | Philipp Zabel <p.zabel@pengutronix.de> | 2017-02-24 18:23:55 +0100 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2017-03-15 15:28:27 +0100 |
| commit | f9bb7acb9b19a40dbd9d1b89380335dc8e23925f (patch) | |
| tree | 78337336d19efb7429f18eb8b88102c31c6007de /drivers/gpu/ipu-v3/ipu-common.c | |
| parent | 2212a780b9c515cd54a5707713307efab9896b4f (diff) | |
| download | linux-f9bb7acb9b19a40dbd9d1b89380335dc8e23925f.tar.gz | |
gpu: ipu-v3: add unsynchronised DP channel disabling
When disabling the foreground DP channel during a modeset, the DC is
already disabled without waiting for end of frame. There is no reason
to wait for a frame boundary before updating the DP registers in that
case.
Add support to apply updates immediately. No functional changes, yet.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'drivers/gpu/ipu-v3/ipu-common.c')
| -rw-r--r-- | drivers/gpu/ipu-v3/ipu-common.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index 8368e6f766ee..8a32ed25a1c2 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -51,15 +51,17 @@ int ipu_get_num(struct ipu_soc *ipu) } EXPORT_SYMBOL_GPL(ipu_get_num); -void ipu_srm_dp_sync_update(struct ipu_soc *ipu) +void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) { u32 val; val = ipu_cm_read(ipu, IPU_SRM_PRI2); - val |= 0x8; + val &= ~DP_S_SRM_MODE_MASK; + val |= sync ? DP_S_SRM_MODE_NEXT_FRAME : + DP_S_SRM_MODE_NOW; ipu_cm_write(ipu, val, IPU_SRM_PRI2); } -EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update); +EXPORT_SYMBOL_GPL(ipu_srm_dp_update); enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) { |