diff options
| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-05-27 23:59:40 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-03 12:27:31 +0100 |
| commit | 9e05bbac43ebfc2fd1ff95e072730ceed807d149 (patch) | |
| tree | c4b588b4b5abea34fe6f04283bff5b157d34caea /drivers/media/i2c/ccs-pll.h | |
| parent | fe652254e243a58daf50aa0ddb938885ae2ba565 (diff) | |
| download | linux-9e05bbac43ebfc2fd1ff95e072730ceed807d149.tar.gz | |
media: smiapp-pll: Rename as ccs-pll
MIPI CCS replaces SMIA and SMIA++ as the current standard. CCS brings new
features while existing functionality will be supported. Rename the
smiapp-pll as ccs-pll accordingly.
Also add Intel copyright to the files.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs-pll.h')
| -rw-r--r-- | drivers/media/i2c/ccs-pll.h | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h new file mode 100644 index 000000000000..88d641ee3fa1 --- /dev/null +++ b/drivers/media/i2c/ccs-pll.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * drivers/media/i2c/ccs-pll.h + * + * Generic MIPI CCS/SMIA/SMIA++ PLL calculator + * + * Copyright (C) 2020 Intel Corporation + * Copyright (C) 2012 Nokia Corporation + * Contact: Sakari Ailus <sakari.ailus@iki.fi> + */ + +#ifndef CCS_PLL_H +#define CCS_PLL_H + +/* CSI-2 or CCP-2 */ +#define CCS_PLL_BUS_TYPE_CSI2 0x00 +#define CCS_PLL_BUS_TYPE_PARALLEL 0x01 + +/* op pix clock is for all lanes in total normally */ +#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) +#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) + +struct ccs_pll_branch { + uint16_t sys_clk_div; + uint16_t pix_clk_div; + uint32_t sys_clk_freq_hz; + uint32_t pix_clk_freq_hz; +}; + +struct ccs_pll { + /* input values */ + uint8_t bus_type; + union { + struct { + uint8_t lanes; + } csi2; + struct { + uint8_t bus_width; + } parallel; + }; + unsigned long flags; + uint8_t binning_horizontal; + uint8_t binning_vertical; + uint8_t scale_m; + uint8_t scale_n; + uint8_t bits_per_pixel; + uint32_t link_freq; + uint32_t ext_clk_freq_hz; + + /* output values */ + uint16_t pre_pll_clk_div; + uint16_t pll_multiplier; + uint32_t pll_ip_clk_freq_hz; + uint32_t pll_op_clk_freq_hz; + struct ccs_pll_branch vt; + struct ccs_pll_branch op; + + uint32_t pixel_rate_csi; + uint32_t pixel_rate_pixel_array; +}; + +struct ccs_pll_branch_limits { + uint16_t min_sys_clk_div; + uint16_t max_sys_clk_div; + uint32_t min_sys_clk_freq_hz; + uint32_t max_sys_clk_freq_hz; + uint16_t min_pix_clk_div; + uint16_t max_pix_clk_div; + uint32_t min_pix_clk_freq_hz; + uint32_t max_pix_clk_freq_hz; +}; + +struct ccs_pll_limits { + /* Strict PLL limits */ + uint32_t min_ext_clk_freq_hz; + uint32_t max_ext_clk_freq_hz; + uint16_t min_pre_pll_clk_div; + uint16_t max_pre_pll_clk_div; + uint32_t min_pll_ip_freq_hz; + uint32_t max_pll_ip_freq_hz; + uint16_t min_pll_multiplier; + uint16_t max_pll_multiplier; + uint32_t min_pll_op_freq_hz; + uint32_t max_pll_op_freq_hz; + + struct ccs_pll_branch_limits vt; + struct ccs_pll_branch_limits op; + + /* Other relevant limits */ + uint32_t min_line_length_pck_bin; + uint32_t min_line_length_pck; +}; + +struct device; + +int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, + struct ccs_pll *pll); + +#endif /* CCS_PLL_H */ |