diff options
| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2013-08-25 16:30:40 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-08-26 14:09:06 -0400 |
| commit | d1ae25a0174938f03e28dee8f3269a826fc1bec5 (patch) | |
| tree | 37b563d41e412267868b4b563d164b0e77197009 /drivers/net/wireless/ath/ath9k/ar9002_hw.c | |
| parent | 8aada63cc408874916a19341ba514f941096e424 (diff) | |
| download | linux-d1ae25a0174938f03e28dee8f3269a826fc1bec5.tar.gz | |
ath9k: Fix ASPM workaround usage
The PCIE Workaround register (AR_WA/0x4004) is used to handle
various hardware quirks. For AR9002 chips, AR_WA_D3_L1_DISABLE
is used to prevent the HW from automatically entering L1 state
when D3 is enforced.
AR_WA_D3_L1_DISABLE has to be enabled for a few AR9280 based
cards, mark them based on their PCI subdevice/subvendor IDs
and enforce it in ar9002_hw_configpcipowersave().
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_hw.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9002_hw.c | 29 |
1 files changed, 11 insertions, 18 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c index 8dc2d089cdef..fb61b081d172 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c @@ -269,13 +269,12 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) val |= AR_WA_D3_L1_DISABLE; } else { - if (((AR_SREV_9285(ah) || - AR_SREV_9271(ah) || - AR_SREV_9287(ah)) && - (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || - (AR_SREV_9280(ah) && - (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { - val |= AR_WA_D3_L1_DISABLE; + if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { + if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE) + val |= AR_WA_D3_L1_DISABLE; + } else if (AR_SREV_9280(ah)) { + if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE) + val |= AR_WA_D3_L1_DISABLE; } } @@ -297,24 +296,18 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, } else { if (ah->config.pcie_waen) { val = ah->config.pcie_waen; - if (!power_off) - val &= (~AR_WA_D3_L1_DISABLE); + val &= (~AR_WA_D3_L1_DISABLE); } else { - if (AR_SREV_9285(ah) || - AR_SREV_9271(ah) || - AR_SREV_9287(ah)) { + if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { val = AR9285_WA_DEFAULT; - if (!power_off) - val &= (~AR_WA_D3_L1_DISABLE); - } - else if (AR_SREV_9280(ah)) { + val &= (~AR_WA_D3_L1_DISABLE); + } else if (AR_SREV_9280(ah)) { /* * For AR9280 chips, bit 22 of 0x4004 * needs to be set. */ val = AR9280_WA_DEFAULT; - if (!power_off) - val &= (~AR_WA_D3_L1_DISABLE); + val &= (~AR_WA_D3_L1_DISABLE); } else { val = AR_WA_DEFAULT; } |