diff options
| author | Stanley Chu <stanley.chu@mediatek.com> | 2021-10-16 08:58:00 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2021-10-18 22:38:35 -0400 |
| commit | fc65e933fbcce09eb6d0b3080694229f6add38bf (patch) | |
| tree | c5b2c37b72ebd91f7046f22830875fd60c90ca42 /drivers/scsi/ufs/ufs-mediatek.c | |
| parent | 1d2ac7b69d6a984d0f58b82d0f658ebd9aa05428 (diff) | |
| download | linux-fc65e933fbcce09eb6d0b3080694229f6add38bf.tar.gz | |
scsi: ufs: ufs-mediatek: Introduce default delay for reference clock
Introduce default delay time for gating or ungating reference clock instead
of ambiguous magic numbers.
The defined value is suitable for all current MediaTek UFS platforms.
Link: https://lore.kernel.org/r/20211016005802.7729-2-stanley.chu@mediatek.com
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/ufs/ufs-mediatek.c')
| -rw-r--r-- | drivers/scsi/ufs/ufs-mediatek.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index d1696db70ce8..2c7d12a30493 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -282,7 +282,7 @@ out: } static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba, - u16 gating_us, u16 ungating_us) + u16 gating_us) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); @@ -293,7 +293,7 @@ static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba, host->ref_clk_gating_wait_us = gating_us; } - host->ref_clk_ungating_wait_us = ungating_us; + host->ref_clk_ungating_wait_us = REFCLK_DEFAULT_WAIT_US; } static void ufs_mtk_dbg_sel(struct ufs_hba *hba) @@ -1102,11 +1102,14 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba) * requirements. */ if (mid == UFS_VENDOR_SAMSUNG) - ufs_mtk_setup_ref_clk_wait_us(hba, 1, 1); + ufs_mtk_setup_ref_clk_wait_us(hba, 1); else if (mid == UFS_VENDOR_SKHYNIX) - ufs_mtk_setup_ref_clk_wait_us(hba, 30, 30); + ufs_mtk_setup_ref_clk_wait_us(hba, 30); else if (mid == UFS_VENDOR_TOSHIBA) - ufs_mtk_setup_ref_clk_wait_us(hba, 100, 32); + ufs_mtk_setup_ref_clk_wait_us(hba, 100); + else + ufs_mtk_setup_ref_clk_wait_us(hba, + REFCLK_DEFAULT_WAIT_US); return 0; } |