diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2022-08-30 12:12:40 +0300 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2022-09-05 09:02:16 +0300 |
| commit | 3846d011403b57190b6b3e917cc8b3ab810fa293 (patch) | |
| tree | bb2e1d46db6ef392faef5dc10d7644052f072ebe /drivers/thunderbolt/switch.c | |
| parent | 95f8f1cbc87bfd361286d8e0129108d2112e653e (diff) | |
| download | linux-3846d011403b57190b6b3e917cc8b3ab810fa293.tar.gz | |
thunderbolt: Pass CL state bitmask to tb_port_clx_supported()
Instead of testing just a single CL state we can pass a bitmask of
states to check. This makes it simpler for callers of the function.
We also add a check for CL2 even though not fully supported by the
driver yet.
Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/switch.c')
| -rw-r--r-- | drivers/thunderbolt/switch.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index deefc92c7c60..0671f5361b5b 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -1259,9 +1259,9 @@ static int tb_port_pm_secondary_disable(struct tb_port *port) } /* Called for USB4 or Titan Ridge routers only */ -static bool tb_port_clx_supported(struct tb_port *port, enum tb_clx clx) +static bool tb_port_clx_supported(struct tb_port *port, unsigned int clx_mask) { - u32 mask, val; + u32 val, mask = 0; bool ret; /* Don't enable CLx in case of two single-lane links */ @@ -1279,17 +1279,12 @@ static bool tb_port_clx_supported(struct tb_port *port, enum tb_clx clx) return false; } - switch (clx) { - case TB_CL1: + if (clx_mask & TB_CL1) { /* CL0s and CL1 are enabled and supported together */ - mask = LANE_ADP_CS_0_CL0S_SUPPORT | LANE_ADP_CS_0_CL1_SUPPORT; - break; - - /* For now we support only CL0s and CL1. Not CL2 */ - case TB_CL2: - default: - return false; + mask |= LANE_ADP_CS_0_CL0S_SUPPORT | LANE_ADP_CS_0_CL1_SUPPORT; } + if (clx_mask & TB_CL2) + mask |= LANE_ADP_CS_0_CL2_SUPPORT; ret = tb_port_read(port, &val, TB_CFG_PORT, port->cap_phy + LANE_ADP_CS_0, 1); |