diff options
| author | Mark Brown <broonie@kernel.org> | 2022-10-19 16:37:01 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-10-19 16:37:01 +0100 |
| commit | 008f05a72d32dcc14038801649ec67af765fcc3c (patch) | |
| tree | c958a2ab7039ea3e03621b1cbae4fcad41ee947c /include/sound/hda_register.h | |
| parent | 32def55d237e8507d4eb8442628fc2e59a899ea0 (diff) | |
| parent | df496157a5afa1b6d1f4c46ad6549c2c346d1e59 (diff) | |
| download | linux-008f05a72d32dcc14038801649ec67af765fcc3c.tar.gz | |
ASoC: jz4752b: Capture fixes
Merge series from Siarhei Volkau <lis8215@gmail.com>:
The patchset fixes:
- Line In path stays powered off during capturing or
bypass to mixer.
- incorrectly represented dB values in alsamixer, et al.
- incorrect represented Capture input selector in alsamixer
in Playback tab.
- wrong control selected as Capture Master
Diffstat (limited to 'include/sound/hda_register.h')
| -rw-r--r-- | include/sound/hda_register.h | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index ad8b71b1dbb6..d37cf43546eb 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -260,7 +260,18 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_ML_LCAP 0x00 #define AZX_REG_ML_LCTL 0x04 + +#define AZX_ML_LCTL_CPA BIT(23) +#define AZX_ML_LCTL_CPA_SHIFT 23 +#define AZX_ML_LCTL_SPA BIT(16) +#define AZX_ML_LCTL_SPA_SHIFT 16 +#define AZX_ML_LCTL_SCF GENMASK(3, 0) + #define AZX_REG_ML_LOSIDV 0x08 + +/* bit0 is reserved, with BIT(1) mapping to stream1 */ +#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE + #define AZX_REG_ML_LSDIID 0x0C #define AZX_REG_ML_LPSOO 0x10 #define AZX_REG_ML_LPSIO 0x12 @@ -268,15 +279,6 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LINPAY 0x30 -/* bit0 is reserved, with BIT(1) mapping to stream1 */ -#define ML_LOSIDV_STREAM_MASK 0xFFFE - -#define ML_LCTL_SCF_MASK 0xF -#define AZX_MLCTL_SPA (0x1 << 16) -#define AZX_MLCTL_CPA (0x1 << 23) -#define AZX_MLCTL_SPA_SHIFT 16 -#define AZX_MLCTL_CPA_SHIFT 23 - /* registers for DMA Resume Capability Structure */ #define AZX_DRSM_CAP_ID 0x5 #define AZX_REG_DRSM_CTL 0x4 |