diff options
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_core.h | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_hti.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 8 |
3 files changed, 15 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 337d8e08ba43..d851d401211f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -371,6 +371,16 @@ struct intel_display { } hdcp; struct { + /* + * HTI (aka HDPORT) state read during initial hw readout. Most + * platforms don't have HTI, so this will just stay 0. Those + * that do will use this later to figure out which PLLs and PHYs + * are unavailable for driver usage. + */ + u32 state; + } hti; + + struct { struct i915_power_domains domains; /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ diff --git a/drivers/gpu/drm/i915/display/intel_hti.c b/drivers/gpu/drm/i915/display/intel_hti.c index 3dfd7203f01c..12a1f4ce1a77 100644 --- a/drivers/gpu/drm/i915/display/intel_hti.c +++ b/drivers/gpu/drm/i915/display/intel_hti.c @@ -16,23 +16,23 @@ void intel_hti_init(struct drm_i915_private *i915) * any display resources before we create our display outputs. */ if (INTEL_INFO(i915)->display.has_hti) - i915->hti_state = intel_de_read(i915, HDPORT_STATE); + i915->display.hti.state = intel_de_read(i915, HDPORT_STATE); } bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy) { - return i915->hti_state & HDPORT_ENABLED && - i915->hti_state & HDPORT_DDI_USED(phy); + return i915->display.hti.state & HDPORT_ENABLED && + i915->display.hti.state & HDPORT_DDI_USED(phy); } u32 intel_hti_dpll_mask(struct drm_i915_private *i915) { - if (!(i915->hti_state & HDPORT_ENABLED)) + if (!(i915->display.hti.state & HDPORT_ENABLED)) return 0; /* * Note: This is subtle. The values must coincide with what's defined * for the platform. */ - return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state); + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display.hti.state); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 05b3300cc4ed..bb88aee2af25 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -301,14 +301,6 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; /* - * HTI (aka HDPORT) state read during initial hw readout. Most - * platforms don't have HTI, so this will just stay 0. Those that do - * will use this later to figure out which PLLs and PHYs are unavailable - * for driver usage. - */ - u32 hti_state; - - /* * edram size in MB. * Cannot be determined by PCIID. You must always read a register. */ |