diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/drm/drm_dp_helper.h | 21 | ||||
| -rw-r--r-- | include/drm/drm_hdcp.h | 8 | ||||
| -rw-r--r-- | include/uapi/drm/drm_fourcc.h | 19 |
3 files changed, 26 insertions, 22 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 6236f212da61..edffd1dcca3e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -2029,16 +2029,13 @@ struct drm_dp_desc { int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, bool is_branch); -u32 drm_dp_get_edid_quirks(const struct edid *edid); /** * enum drm_dp_quirk - Display Port sink/branch device specific quirks * * Display Port sink and branch devices in the wild have a variety of bugs, try * to collect them here. The quirks are shared, but it's up to the drivers to - * implement workarounds for them. Note that because some devices have - * unreliable OUIDs, the EDID of sinks should also be checked for quirks using - * drm_dp_get_edid_quirks(). + * implement workarounds for them. */ enum drm_dp_quirk { /** @@ -2071,16 +2068,6 @@ enum drm_dp_quirk { */ DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, /** - * @DP_QUIRK_FORCE_DPCD_BACKLIGHT: - * - * The device is telling the truth when it says that it uses DPCD - * backlight controls, even if the system's firmware disagrees. This - * quirk should be checked against both the ident and panel EDID. - * When present, the driver should honor the DPCD backlight - * capabilities advertised. - */ - DP_QUIRK_FORCE_DPCD_BACKLIGHT, - /** * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: * * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite @@ -2092,16 +2079,14 @@ enum drm_dp_quirk { /** * drm_dp_has_quirk() - does the DP device have a specific quirk * @desc: Device descriptor filled by drm_dp_read_desc() - * @edid_quirks: Optional quirk bitmask filled by drm_dp_get_edid_quirks() * @quirk: Quirk to query for * * Return true if DP device identified by @desc has @quirk. */ static inline bool -drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks, - enum drm_dp_quirk quirk) +drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) { - return (desc->quirks | edid_quirks) & BIT(quirk); + return desc->quirks & BIT(quirk); } #ifdef CONFIG_DRM_DP_CEC diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index fe58dbb46962..ac22c246542a 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -101,11 +101,11 @@ /* Following Macros take a byte at a time for bit(s) masking */ /* - * TODO: This has to be changed for DP MST, as multiple stream on - * same port is possible. - * For HDCP2.2 on HDMI and DP SST this value is always 1. + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual + * H/W MST streams capacity. + * This required to be moved out to platform specific header. */ -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4 #define HDCP_2_2_TXCAP_MASK_LEN 2 #define HDCP_2_2_RXCAPS_LEN 3 #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 5f42a14481bd..f76de49c768f 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -528,6 +528,25 @@ extern "C" { #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) /* + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render + * compression. + * + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear + * and at index 1. The clear color is stored at index 2, and the pitch should + * be ignored. The clear color structure is 256 bits. The first 128 bits + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented + * by 32 bits. The raw clear color is consumed by the 3d engine and generates + * the converted clear color of size 64 bits. The first 32 bits store the Lower + * Converted Clear Color value and the next 32 bits store the Higher Converted + * Clear Color value when applicable. The Converted Clear Color values are + * consumed by the DE. The last 64 bits are used to store Color Discard Enable + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line + * corresponds to an area of 4x1 tiles in the main surface. The main surface + * pitch is required to be a multiple of 4 tile widths. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) + +/* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * * Macroblocks are laid in a Z-shape, and each pixel data is following the |