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* drivers: clk: st: Fix FSYN channel valuesGabriel Fernandez2015-07-061-2/+2
| | | | | | | | | This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* drivers: clk: st: Remove unused codeGabriel Fernandez2015-07-061-4/+0
| | | | | | | Remove this duplicated code due to a bad copy / paste. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Use parent rate when set rate to pixel RCG clockHai Li2015-07-061-6/+3
| | | | | | | | | | | | Since the parent rate has been recalculated, pixel RCG clock should rely on it to find the correct M/N values during set_rate, instead of calling __clk_round_rate() to its parent again. Signed-off-by: Hai Li <hali@codeaurora.org> Tested-by: Archit Taneja <architt@codeaurora.org> Fixes: 99cbd064b059 ("clk: qcom: Support display RCG clocks") [sboyd@codeaurora.org: Silenced unused parent variable warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: do not leak resourcesDavid Dueck2015-07-026-10/+30
| | | | | | | | Do not leak memory and free irqs in case of an error. Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: David Dueck <davidcdueck@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: stm32: Fix out-by-one error path in the index lookupDaniel Thompson2015-07-021-1/+1
| | | | | | | | | | | | | | | | If stm32f4_rcc_lookup() is called with primary == 0 and secondary == 192 then it will read beyond the end of the table array due to an out-by-one error in the range check. In addition to the fixing the inequality we also modify the r.h.s. to make it even more explicit that we are comparing against the size of table in bits. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Fixes: 358bdf892f6b ("clk: stm32: Add clock driver for STM32F4[23]xxx devices") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: iproc: fix bit manipulation arithmeticRay Jui2015-07-021-2/+3
| | | | | | | | | | A 32-bit variable should be type casted to 64-bit before arithmetic operation and assigning it to a 64-bit variable Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: iproc: fix memory leak from clock nameRay Jui2015-07-022-12/+2
| | | | | | | | | | | | | | of_property_read_string_index takes array of pointers and assign them to strings read from device tree property. No additional memory allocation is needed prior to calling of_property_read_string_index. In fact, since the array of pointers will be re-assigned to other strings, any memory that it points to prior to calling of_property_read_string_index will be leaked Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: stm32: Add clock driver for STM32F4[23]xxx devicesDaniel Thompson2015-06-222-0/+381
| | | | | | | | | | | | | | | | | | | The driver supports decoding and statically modelling PLL state (i.e. we inherit state from bootloader) and provides support for all peripherals that support simple one-bit gated clocks. The covers all peripherals whose clocks come from the AHB, APB1 or APB2 buses. It has been tested on an STM32F429I-Discovery board. The clock counts for TIM2, USART1 and SYSTICK are all set correctly and the wall clock looks OK when checked with a stopwatch. I have also tested a prototype driver for the RNG hardware. The RNG clock is correctly enabled by the framework (also did inverse test and proved that by changing DT to configure the wrong clock bit then we observe the RNG driver to fail). Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> [sboyd@codeaurora.org: Silence sparse warnings] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* dt-bindings: Document the STM32F4 clock bindingsDaniel Thompson2015-06-221-0/+65
| | | | | | | | | This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'tegra-for-4.2-clk' of ↵Michael Turquette2015-06-2013-16/+637
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.2-rc1 This contains the EMC clock driver that's been exhaustively reviewed and tested. It also includes a change to the clock core that allows a clock provider to perform low-level reparenting of clocks. This is required by the EMC clock driver because the reparenting needs to be done at a very specific point in time during the EMC frequency switch.
| * clk: tegra: Fix hda2codec_2x clock name for Tegra30Marcel Ziswiler2015-05-131-1/+1
| | | | | | | | | | | | | | | | The HDA to codec clock is named hda2codec_2x, so use the proper name in the clock table. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: EMC clock driver depends on EMC driverThierry Reding2015-05-134-1/+15
| | | | | | | | | | | | | | The EMC clock driver uses symbols exported by the EMC driver, so it needs the corresponding dependency to avoid build breakage. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Have EMC clock implement determine_rate()Tomeu Vizoso2015-05-131-12/+23
| | | | | | | | | | | | | | | | As opposed to round_rate(), determine_rate() can take rate constraints into account when choosing the best rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Set the EMC clock as the parent of the MC clockTomeu Vizoso2015-05-131-12/+1
| | | | | | | | | | | | | | On Tegra124, as we now have a proper driver for the EMC. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Add EMC clock driverMikko Perttunen2015-05-134-2/+535
| | | | | | | | | | | | | | | | | | | | | | | | The driver is currently only tested on Tegra124 Jetson TK1, but should work with other Tegra124 boards, provided that correct EMC tables are provided through the device tree. Older chip models have differing timing change sequences, so they are not currently supported. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> [treding@nvidia.com: use more consistent function names] Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Remove old Tegra124 EMC clockMikko Perttunen2015-05-131-1/+0
| | | | | | | | | | | | | | | | This clock has never been able to do anything. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * of: document external-memory-controller property in tegra124-carTomeu Vizoso2015-05-131-0/+2
| | | | | | | | | | | | | | | | | | This property contains a phandle to the EMC driver that is needed by the EMC clock to request the EMC driver to do its part of the clock change sequence. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * of: document new emc-timings subnode in nvidia,tegra124-carTomeu Vizoso2015-05-131-1/+41
| | | | | | | | | | | | | | The EMC clock needs some extra information for changing its rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: Expose clk_hw_reparent() to providersTomeu Vizoso2015-05-132-0/+9
| | | | | | | | | | | | | | | | To be used by clock implementations for switching to a new parent during rate change. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * Merge branch 'for-4.2/ramcode' into for-4.2/clkThierry Reding2015-05-133-0/+24
| |\
| | * soc/tegra: fuse: Add RAM code reader helperMikko Perttunen2015-05-042-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * of: Document long-ram-code property in nvidia,tegra20-apbmiscTomeu Vizoso2015-05-041-0/+2
| |/ | | | | | | | | | | | | Needed to properly decode the RAM code register. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge branch 'clk-exynos-cpu-clk' into clk-nextMichael Turquette2015-06-2012-212/+471
|\ \ | | | | | | | | | | | | Folded into this merge commit is a build error fix: s/clk/core in clk_change_rate due to the new struct clk_core
| * | cpufreq: exynos: remove Exynos4210 specific cpufreq driver supportThomas Abraham2015-06-205-209/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos4210 based platforms have switched over to use generic cpufreq driver for cpufreq functionality. So the Exynos specific cpufreq support for these platforms can be removed. Changes by Bartlomiej: - dropped Exynos5250 support removal for now - updated exynos-cpufreq.[c,h] Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | ARM: Exynos: switch to using generic cpufreq driver for Exynos4210Thomas Abraham2015-06-201-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new CPU clock type allows the use of generic CPUfreq driver. Switch Exynos4210 to using generic cpufreq driver. Changes by Bartlomiej: - removed non-Exynos4210 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu ↵Thomas Abraham2015-06-201-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210. Changes by Bartlomiej: - fixed issue with wrong dividers being setup by Common Clock Framework (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock, without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board), this was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags") but using these flags is not sufficient to fix the issue observed - removed Exynos5250 and Exynos5420 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | clk: samsung: add infrastructure to register cpu clocksThomas Abraham2015-06-203-1/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms. Changes by Bartlomiej: - fixed issue with setting lower dividers before the parent clock speed was lowered (the issue resulted in lockup on Exynos4210 SoC based Origen board when "ondemand" cpufreq governor was stress tested) - fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change() problem by moving cfg_data search outside of the spin locked area - removed leftover kfree() in exynos_register_cpu_clock() that could result in dereferencing the NULL pointer on error - moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers - added missing "last chance" checks to wait_until_divider_stable() and wait_until_mux_stable() (needed in case that IRQ handling took long time to proceed and resulted in function printing incorrect error message about timeout) - moved E4210_CPU_DIV[0,1]() macros just before their only users, this resulted in moving them from patch #2 to patch #3/6 ("clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock") - removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV() macros for now - added my Copyrights to drivers/clk/samsung/clk-cpu.c Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock supportBartlomiej Zolnierkiewicz2015-06-202-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is needed to fix the issue with wrong dividers being setup by Common Clock Framework when using the new Exynos cpu clock support. The issue happens because clk_core_set_rate_nolock() calls clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have a chance to run. In case of Exynos cpu clock support pre/post clock notifiers are registered for mout_apll clock which is a parent of armclk cpu clock and dividers are modified in both pre and post clock notifier. This results in wrong dividers values being later programmed by clk_change_rate(top). To workaround the problem CLK_RECALC_NEW_RATES flag is added and it is set for mout_apll clock later so the correct divider values are re-calculated after both pre and post clock notifiers had run. For example when using "performance" governor on Exynos4210 Origen board the cpufreq-dt driver requests to change the frequency from 1000MHz to 1200MHz and after the change state of the relevant clocks is following: Without use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 300000000 div_hpm rate: 300000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 300000000 div_pclk_dbg rate: 150000000 sclk_apll rate: 1200000000 sclk_apll_div_2 rate: 600000000 With use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 200000000 div_hpm rate: 200000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 240000000 div_pclk_dbg rate: 120000000 sclk_apll rate: 150000000 sclk_apll_div_2 rate: 75000000 Without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board. This issue was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags" patch) but usage of these flags is not sufficient to fix the issue observed. Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | doc: dt: add documentation for lpc1850-ccu clk driverJoachim Eastwood2015-06-181-0/+77
| | | | | | | | | | | | | | | | | | | | | Add DT binding documentation for lpc1850-ccu clk driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: add lpc18xx ccu clk driverJoachim Eastwood2015-06-183-0/+368
| | | | | | | | | | | | | | | | | | | | | | | | Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU provides fine grained gating of most clocks present in the SoC. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | doc: dt: add documentation for lpc1850-cgu clk driverJoachim Eastwood2015-06-181-0/+131
| | | | | | | | | | | | | | | | | | | | | Add DT binding documentation for lpc1850-cgu driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: add lpc18xx cgu clk driverJoachim Eastwood2015-06-184-0/+678
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU contains several clock generators and output stages that route the clocks either directly to peripherals or to a Clock Control Unit (CCU). Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: keystone: add support for post divider register for main pllMurali Karicheri2015-06-182-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | Merge tag 'sunxi-clocks-for-4.2' of ↵Michael Turquette2015-06-184-5/+19
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks additions for 4.2 One error fix, and one patch to add support for the USB clock found on the Allwinner A23 and A33
| * | | clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCsHans de Goede2015-06-022-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic interface which gets enabled by almost the same bits as used on the a31 for the 3rd phy, but not exactly the same bits so we need a new compatible for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
| * | | clk: sunxi: Fix of_io_request_and_map error checkMaxime Ripard2015-05-052-5/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_io_request_and map returns an error pointer, but the current code assumes that on error the returned pointer will be NULL. Obviously, that makes the check completely useless. Change the test to actually check for the proper error code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org
* | | clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSEDBoris Brezillon2015-06-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The crypto SRAM, used by the armada 370 cpuidle code to workaround a bug in the BootROM code, requires the crypto clk to be up and running. Flag the crypto clk as IGNORE_UNUSED until we add the proper infrastructure to define the crypto SRAM in the DT and reference the crypto clk in this SRAM node. Reported-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: cygnus: remove Cygnus dummy clock bindingRay Jui2015-06-181-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove old Cygnus dummy clock binding document, as it's replaced by Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: cygnus: add clock support for Broadcom CygnusRay Jui2015-06-183-0/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom Cygnus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied from an onboard crystal. Cygnus also has various ASIU clocks that are derived directly from the onboard crystal. Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: Change bcm clocks build dependencyRay Jui2015-06-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock code under drivers/clk/bcm now contains code for both the Broadcom mobile SoCs and the iProc SoCs. Change the the makefile dependency to be under config flag CONFIG_ARCH_BCM that's enabled for both families of SoCs Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: iproc: add initial common clock supportRay Jui2015-06-186-0/+1462
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic and generic support for various iProc PLLs and clocks including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks. SoCs under the iProc architecture can define their specific register offsets and clock parameters for their PLL and clock controllers. These parameters can be passed as arugments into the generic iProc PLL and clock setup functions Derived from code originally provided by Jonathan Richardson <jonathar@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | clk: iproc: define Broadcom iProc clock bindingRay Jui2015-06-181-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | Document the device tree binding for Broadcom iProc architecture based clock controller Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | MAINTAINERS: update email for Michael TurquetteMichael Turquette2015-06-171-1/+1
| | | | | | | | | | | | Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | Merge branch 'clk-shmobile-for-4.2' of ↵Michael Turquette2015-06-174-6/+10
|\ \ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
| * | | clk: shmobile: rz: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic RZ CPG compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: shmobile: rcar-gen2: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic R-Car Gen2 CPG compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: shmobile: mstp: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic MSTP gate clocks compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Also fix a typo (missing plural "s") in the compatible value. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: shmobile: div6: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic CPG DIV6 clock compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: shmobile: r8a7794: Document DIV6 clock bindingsGeert Uytterhoeven2015-06-011-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: shmobile: r8a7793: Document DIV6 clock bindingsUlrich Hecht2015-06-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Cc: devicetree@vger.kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-02-25 20:29:24 +0000