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Pull arm-soc driver specific updates from Olof Johansson:
"These changes are specific to some driver that may be used by multiple
boards or socs. The most significant change in here is the move of
the samsung iommu code from a platform specific in-kernel interface to
the generic iommu subsystem."
Fix up trivial conflicts in arch/arm/mach-exynos/Kconfig
* tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
mmc: dt: Consolidate DT bindings
iommu/exynos: Add iommu driver for EXYNOS Platforms
ARM: davinci: optimize the DMA ISR
ARM: davinci: implement DEBUG_LL port choice
ARM: tegra: Add SMMU enabler in AHB
ARM: tegra: Add Tegra AHB driver
Input: pxa27x_keypad add choice to set direct_key_mask
Input: pxa27x_keypad direct key may be low active
Input: pxa27x_keypad bug fix for direct_key_mask
Input: pxa27x_keypad keep clock on as wakeup source
ARM: dt: tegra: pinmux changes for USB ULPI
ARM: tegra: add USB ULPI PHY reset GPIO to device tree
ARM: tegra: don't hard-code USB ULPI PHY reset_gpio
ARM: tegra: change pll_p_out4's rate to 24MHz
ARM: tegra: fix pclk rate
ARM: tegra: reparent sclk to pll_c_out1
ARM: tegra: Add pllc clock init table
ARM: dt: tegra cardhu: basic audio support
ARM: dt: tegra30.dtsi: Add audio-related nodes
ARM: tegra: add AUXDATA required for audio
...
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
* 'next/devel-samsung-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
iommu/exynos: Add iommu driver for EXYNOS Platforms
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This is the System MMU driver and IOMMU API implementation for
EXYNOS SoC platforms. EXYNOS platforms has more than 10 System
MMUs dedicated for each multimedia accelerators.
The System MMU driver is already in arc/arm/plat-s5p but it is
moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU
drivers there.
Any device driver in EXYNOS platforms that needs to control its
System MMU must call platform_set_sysmmu() to inform System MMU
driver who will control it. platform_set_sysmmu() is defined in
<mach/sysmmu.h>
Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
Acked-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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* drivers/mmc:
mmc: dt: Consolidate DT bindings
Also pulls in the omap/dt-missed-3.4 branch as a dependency.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This patch unifies the current DT MMC bindings documentation and code,
adds generic MMC DT bindings documentation, and updates .dts files for
consistency.
[cjb: typo fixes, addition of max-frequency property]
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The omap/dt branch adds a few instances of mmc device nodes that
need to get changed to use the common bindings. Pull that into
a new branch so we can apply the patch in a single run.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
* tegra/ahb:
ARM: tegra: Add SMMU enabler in AHB
ARM: tegra: Add Tegra AHB driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add extern func, "tegra_ahb_enable_smmu()" to inform AHB that SMMU is
ready.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
High-performance Bus (AHB) architecture.
The AHB Arbiter controls AHB bus master arbitration. This effectively
forms a second level of arbitration for access to the memory
controller through the AHB Slave Memory device. The AHB pre-fetch
logic can be configured to enhance performance for devices doing
sequential access. Each AHB master is assigned to either the high or
low priority bin. Both Tegra20/30 have this AHB bus.
Some of configuration params could be passed from DT too if needed.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
* 'next/cleanup-samsung-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Change System MMU platform device definitions
S5P: SYSMMU: Remove System MMU device driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Handling System MMUs with an identifier is not flexible to manage
System MMU platform devices because of the following reasons:
1. A device driver which needs to handle System MMU must know the ID.
2. A System MMU may not present in some implementations of Exynos family.
3. Handling System MMU with IOMMU API does not require an ID.
This patch is the result of removing ID of System MMUs.
Instead, a device driver that needs to handle its System MMU must
use IOMMU API while its descriptor of platform device is given.
This patch also includes the following enhancements:
- A System MMU device becomes a child if its power domain device.
- clkdev
Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch removes System MMU device driver from arm/plat-s5p tree
for transition to implement IOMMU driver.
Although controlling System MMU in this removing driver
is similar to the new IOMMU driver in the following patch,
the new one is almost rewrite of this driver and there is no
benefit to moving the driver file from arch/arm/ to drivers/iommu.
Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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into next/drivers
Branch has one driver feature and one board bug fix. Merging it as a driver branch.
DMA driver change was later:
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
* tag 'ep93xx-fixes-for-3.5' of git://github.com/RyanMallon/linux-ep93xx:
dmaengine/ep93xx_dma: Implement double buffering for M2M DMA channels
arm: ep93xx: Don't try to release not acquired GPIO lines
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Add double buffering support for M2M DMA channels. Implement this by using EP93xx
M2M DMA Buffer and Control Finite State Machines to be sure that we are not
disabling the channel when it's actually operating.
Signed-off-by: Rafal Prylowski <prylowski@metasoft.pl>
Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Mika Westerberg <mika.westerberg@iki.fi>
Signed-off-by: Ryan Mallon <rmallon@gmail.com>
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Fail path of ep93xx_keypad_acquire_gpio() tries to release
GPIO lines not acquired successfully before. Fix this.
Signed-off-by: Rafal Prylowski <prylowski@metasoft.pl>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Ryan Mallon <rmallon@gmail.com>
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next/drivers
DaVinci SoC updates for v3.5
This pull request updates the DaVinci SoC support to implement DEBUG_LL port
choice and optimizes the DMA ISR by removing unnecessary register reads.
* tag 'v3.5-soc' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: optimize the DMA ISR
ARM: davinci: implement DEBUG_LL port choice
+ sync with Linux 3.4-rc6
Signed-off-by: Olof Johansson <olof@lixom.net>
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The ISR does quiete a lot of hw access which could be avoided. First it
checks for a pending interrupt by reading alteast one register. Then it
checks for the "activated" slots by reading another register. This is
more or a less a must.
Now, once it found an active slot it does the same two reads again.
After that it "knows" that there must be a pending transfer however it
cross checks with the other register. There are 32 bit in an interger
which are polled instead of considering only the set bits and ignoring
those which are zero. This performs atleast 32 reads which could be
avoided. In case of a first match it does another read.
This patch reorganizes the access by re-using the register which have
been read and then uses ffs() to find the matching slot instead looping
over it. By doing this we get rid of the last (32 + 2 + hits) reads.
It is possible however that by really busy bank0 we never get to handle
bank1. If this is a problem, we could try to handle bank1 after we are
done with bank0 to check if there are any outstanding transfers.
To put some numbers on this, this is from spi transfer via spidev. The
first column is the number of total transfers, the time stamp is taken
before and after the ioctl():
|10000, min: 542us avg: 591us
|20000, min: 542us avg: 592us
|30000, min: 542us avg: 592us
|40000, min: 542us avg: 585us
|50000, min: 542us avg: 593us
The same test case with the patch applied
|10000, min: 444us avg: 493us
|20000, min: 444us avg: 491us
|30000, min: 444us avg: 489us
|40000, min: 444us avg: 491us
|50000, min: 444us avg: 492us
that is almost 100us that just went away.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Apart from the necessity to do this change for multi-platform kernels
the previous logic depended on the zImage decompressor to write the
physical and virtual address to a magic memory location.
If the decompressor is unused or not correctly configured for the
current machid, the addruart macro was an infinite loop. Moreover
debugging the early zImage code was not possible either.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
[nsekhar@ti.com: add braces in _DEBUG_LL_ENTRY() macro to fix checkpatch
error. Fix debug port choice config dependency for traditional DaVincis.
Modify debug port config names and add help text.]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
By Stephen Warren
via Stephen Warren
* 'for-3.5/debug' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: uncompress.h: Implement TEGRA_DEBUG_UART_AUTO_ODMDATA
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Tegra has 5 UARTS which could be used for low-level debug output. Commit
fe26398 "ARM: tegra: uncompress.h: Choose a UART at runtime" implemented
one method for the kernel to automatically determine which of these to
use at run-time, so that the same DEBUG_LL-enabled kernel image could be
used across multiple Tegra boards. The required bootloader-side setup for
that option is implemented in NVIDIA's various downstream U-Boot branches,
but the U-Boot maintainers have refused to accept it upstream.
This change implements an alternative automatic UART selection option
using ODMDATA. This is a 32-bit value programmed into Tegra's boot memory
which provides a few pieces of basic board-specific information, including
a field that indicates the console UART. Setting up this value is part of
the standard Tegra boot architecture, and so requires no Tegra-specific
hacks in the bootloader's UART driver.
Note that in theory, the format of ODMDATA is board-specific. However, in
practice all boards use the same location/size/values for the UART field.
ODMDATA[19:18] (which drive the type of debug console) is more problematic,
since some boards use value 2 for UART and others use 3. This patch just
accepts either value; if this doesn't work well for a given board, I'd
suggest simply not enabling this debug option when building for that board.
Note that the kernel assumes the bootloader has already set up any required
pinmux settings for the UART; there is no way the kernel can do this for
itself prior to knowing which board it's running on. In practice, people
using this feature are highly likely to be using bootloaders that have
indeed configured the pinmux. This assumption existed prior to this patch.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
By Stephen Warren (5) and Peter De Schrijver (1)
via Stephen Warren
* 'for-3.5/tegra30-audio' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: dt: tegra cardhu: basic audio support
ARM: dt: tegra30.dtsi: Add audio-related nodes
ARM: tegra: add AUXDATA required for audio
ARM: tegra: set up audio clocks for tegra30 dt
ARM: tegra: Initialize pll_p_out1
ARM: tegra: provide clock aliases for AHUB configlink
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add WM8903 codec nodes, and top-level sound complex node for basic
analog audio over headset jack and internal speakers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
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Add nodes for the Tegra30 AHUB and I2S controllers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
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Both the Tegra30 I2S and AHUB modules used clocks, and hence currently
require AUXDATA in order to get specific device names so that clock
lookups work.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
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Set up the audio clock tree for Tegra30 in an equivalent fashion to the
existing setup for Tegra20.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
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pll_a uses pll_p_out1 as its parent. Therefore this clock needs to be
initialized to make sure pll_a has a known input clock. Failure to do so
will cause the system to crash early in the bootup.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The Tegra30 AHUB driver must call tegra_periph_reset_deassert() for all
devices on the AHUB's configlink bus. The AHUB driver must be able to
call clk_get_sys() to retrieve the clock parameter for this function.
Add the necessary clock aliases to allow this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
By Stephen Warren (30) and others
via Stephen Warren
* 'for-3.5/usb-ulpi' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (7 commits)
ARM: dt: tegra: pinmux changes for USB ULPI
ARM: tegra: add USB ULPI PHY reset GPIO to device tree
ARM: tegra: don't hard-code USB ULPI PHY reset_gpio
ARM: tegra: change pll_p_out4's rate to 24MHz
ARM: tegra: fix pclk rate
ARM: tegra: reparent sclk to pll_c_out1
ARM: tegra: Add pllc clock init table
+ depends/pinctrl/mergebase branch
Pinctrl mergebase has a conflict in drivers/pinctrl/core.c that was resolved.
Signed-off-by: Olof Johansson <olof@lixom.net>
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Ensure that the USB ULPI signals are not tri-stated, and have no pull-
up or pull-down.
Ensure that the pingroup hosting the USB ULPI reset signal (GPIO PV0 or
PV1 depending on the board, so UAC) is not tri-stated, and has no pull-
up or pull-down.
This change appears larger than it is due to the grouping and sorting of
the pin configuration data.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.
I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have explicit separate
nodes for the various PHYs. However, we don't have that right now, so this
binding seems like a reasonable choice.
Cc: <devicetree-discuss@lists.ozlabs.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of
hard-coding this GPIO into devices.c, make the board files set it
explicitly. This will allow the PHY code to differentiate between set and
unset values, and hence know when to read the value from device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.
Remove board-paz00.c's now-duplicate initialization of this clock.
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the
rate of hclk. Since pclk is derived from that, and only has integer
dividers, the pclk rate needs to change in the same fashion, from 54MHz
to 60MHz.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[]
so that it's possible to explicitly initialize the PLL.
NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different
pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output,
whereas the ChromeOS kernel contains entries for 600MHz output. I chose
to upstream the ChromeOS values for now, since the 600MHz rate appears
to match the default rate of this PLL when the HW boots, and it's not
clear to me why 522 or 598MHz are more useful.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Olof Johansson <olofj@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
[swarren: wrote commit description]
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From Haojian Zhuang <haojian.zhuang@gmail.com>
* 'keyboard' of git://github.com/hzhuang1/linux:
Input: pxa27x_keypad add choice to set direct_key_mask
Input: pxa27x_keypad direct key may be low active
Input: pxa27x_keypad bug fix for direct_key_mask
Input: pxa27x_keypad keep clock on as wakeup source
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Direct keys usage may not start from KP_DKIN0, add a msk option
to configure the specifics for platforms that can skip some keys.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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KPDK_DK only indicates the pin level of direct key.
So it is related to board, and low level may be active which
indicates that a key is pressed.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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When direcct_key_num is 0, the mask should be 0.
When direcct_key_num is 1, the mask should be 0b1.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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When the keypad is used as wake up source, the clock can not
be disabled. Or it can not detect key pressing.
If the keypad is used as wake up source, when resume back,
do not enable the clock and configure it again because the
register content is retained.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc defconfig updates from Olof Johansson:
"For the first time, we have one branch that collects just updates to
defconfig files, mostly for adapting to changes in other subsystems."
* tag 'defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: PRIMA2: add prima2_defconfig for CSR SiRFprimaII
ARM: tegra: update defconfig
ARM: tegra: update defconfig
ARM: imx_v6_v7_defconfig: Add SPI NOR support
ARM: imx_v4_v5_defconfig: Let CONFIG_MACH_IMX27_DT be built by default
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Signed-off-by: Barry Song <Baohua.Song@csr.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/defconfig
* 'for-3.5/defconfig2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: update defconfig
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New options enabled:
* REGULATOR_TPS62360: for Cardhu's CPU core
* MEMORY: dependency for TEGRA*_MC
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> # (parts)
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> # (parts)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/defconfig
By Stephen Warren
via Stephen Warren
* 'for-3.5/defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: update defconfig
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New options enabled:
* RUNTIME_PM
* ISL29028 (light and proximity)
* INPUT_MPU3050 (gyro)
* BATTERY_SBS
* EM3027 RTC
* INPUT_MISC (dependency)
* POWER_SUPPLY (dependency)
The IIO option seems to have been moved recently too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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next/defconfig
ARM i.MX defconfig updates for 3.5
* tag 'imx-defconfig' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM: imx_v6_v7_defconfig: Add SPI NOR support
ARM: imx_v4_v5_defconfig: Let CONFIG_MACH_IMX27_DT be built by default
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Add SPI NOR support in defconfig.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Let CONFIG_MACH_IMX27_DT be built by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
Pull x86/mce merge window patches from Tony Luck:
"Including two that make error_context() checks less sucky"
* tag 'x86-mce-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
x86/mce: Add instruction recovery signatures to mce-severity table
x86/mce: Fix check for processor context when machine check was taken.
MCE: Fix vm86 handling for 32bit mce handler
x86/mce Add validation check before GHES error is recorded
x86/mce: Avoid reading every machine check bank register twice.
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