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* pinctrl/amd: poll InterruptEnable bits in enable_irqDaniel Kurtz2018-03-261-0/+9
| | | | | | | | | | | | | | | | | In certain cases interrupt enablement will be delayed relative to when the InterruptEnable bits are written. One example of this is when a GPIO's "debounce" logice is first enabled. After enabling debounce, there is a 900 us "warm up" period during which InterruptEnable[0] (bit 11) will read as 0 despite being written 1. During this time InterruptSts will not be updated, nor will interrupts be delivered, even if the GPIO's interrupt configuration has been written to the register. To work around this delay, poll the InterruptEnable bits after setting them to ensure interrupts have truly been enabled in hardware before returning from the irq_enable handler. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: ocelot: fix gpio directionAlexandre Belloni2018-03-261-1/+1
| | | | | | | | | | | Bits have to be cleared in DEVCPU_GCB:GPIO:GPIO_OE for input and set for output. ocelot_gpio_set_direction() got it wrong and this went unnoticed when the driver was reworked. Reported-by: Gregory Clement <gregory.clement@bootlin.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mtk: fix check warnings.Zhiyong Tao2018-03-265-1604/+802
| | | | | | | This patch fixes check warnings. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pintcrl: mtk: support bias-disable of generic and special pins simultaneouslyZhiyong Tao2018-03-261-2/+6
| | | | | | | | | | | | For generic pins, parameter "arg" is 0 or 1. For special pins, bias-disable is set by R0R1, so we need transmited "00" to set bias-disable When we set "bias-disable" as high-z property, the parameter should be "MTK_PUPD_SET_R1R0_00". Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: add mt2712 pinctrl driverZhiyong Tao2018-03-264-0/+2398
| | | | | | | | The commit includes mt2712 pinctrl driver. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Reviewed-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0David Lechner2018-03-261-3/+19
| | | | | | | | | | | This fixes pcs_request_gpio() in the pinctrl-single driver when bits_per_mux != 0. It appears this was overlooked when the multiple pins per register feature was added. Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Signed-off-by: David Lechner <david@lechnology.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: imx: Add pinctrl driver support for imx6sllBai Ping2018-03-233-0/+368
| | | | | | | | | Add pinctrl driver support for imx6sll. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* dt-bindings: imx: update pinctrl doc for imx6sllBai Ping2018-03-231-0/+40
| | | | | | | | | Add pinctrl binding doc update for imx6sll. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Implement intel_gpio_get_direction callbackJavier Arteaga2018-03-231-0/+19
| | | | | | | | | | Allows querying GPIO direction from the pad config register. If the pad is not in GPIO mode, return an error. Signed-off-by: Javier Arteaga <javier@emutex.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependencyMasahiro Yamada2018-03-231-6/+6
| | | | | | | | | | | | These configs select MFD_SYSCON, but do not depend on HAS_IOMEM. Compile testing on architecture without HAS_IOMEM causes "unmet direct dependencies" in Kconfig phase. Detected by "make ARCH=score allyesconfig". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mediatek: mtk-common: use true and false for boolean valuesGustavo A. R. Silva2018-03-231-2/+2
| | | | | | | | | Assign true or false to boolean variables instead of an integer value. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: always look for apb blockAndre Przywara2018-03-231-1/+2
| | | | | | | | | | | | | | The Allwinner pinctrl device tree binding suggests that a clock named "apb" would drive the pin controller IP. However (for legacy reasons) we rely on this clock actually being the first clock defined. Since named clocks can be in any order, let's explicitly check for a clock called "apb" if there is more than one clock referenced. Kudo to Maxime for suggesting this much more elegant approach. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: nomadik: Drop U8540/9540 supportLinus Walleij2018-03-237-2376/+17
| | | | | | | | | | | The U8540 was an evolved version of the U8500, but it was never mass produced or put into products, only reference designs exist. The upstream support was never completed and it is unlikely that this will happen so drop the support for now to simplify maintenance of the U8500. Cc: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'sh-pfc-for-v4.17-tag2' of ↵Linus Walleij2018-03-2313-635/+3199
|\ | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 (take two) - Add USB pin groups on R-Car M3-N, - Add support for the new R-Car V3H SoC, - Add EtherAVB pin groups on R-Car V3M, - Miscellaneous fixes and cleanups.
| * pinctrl: sh-pfc: r8a77995: Deduplicate VIN4 pin definitionsUlrich Hecht2018-03-211-118/+36
| | | | | | | | | | | | | | | | Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitionsUlrich Hecht2018-03-211-236/+72
| | | | | | | | | | | | | | | | Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitionsUlrich Hecht2018-03-211-236/+72
| | | | | | | | | | | | | | | | Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77995: Correct VIN4 18-bit pinsUlrich Hecht2018-03-211-6/+6
| | | | | | | | | | | | | | | | RGB666 has a pin assignment that differs from the other formats. Fixes: fbd452aeb49e552e ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function") Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Correct VIN4 18-bit pinsUlrich Hecht2018-03-211-12/+12
| | | | | | | | | | | | | | | | RGB666 has a pin assignment that differs from the other formats. Fixes: 8db6cbabac4f2a02 ("pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions") Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Correct VIN4 18-bit pinsUlrich Hecht2018-03-211-12/+12
| | | | | | | | | | | | | | | | RGB666 has a pin assignment that differs from the other formats. Fixes: 6b4de408105fc51e ("pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions") Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77995: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 66abd968d0ef3eb1 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * pinctrl: sh-pfc: r8a77965: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: fa3e8b71b955af86 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * pinctrl: sh-pfc: r8a7796: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 41397032c4a17dff ("pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins") Fixes: 9c99a63ec74f34f7 ("pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * pinctrl: sh-pfc: r8a7795-es1: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: b25719eb938eb39a ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins") Fixes: 819fd4bfcc84805c ("pinctrl: sh-pfc: r8a7795: add EtherAVB support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * pinctrl: sh-pfc: r8a7795: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven2018-03-211-4/+6
| | | | | | | | | | | | | | | | | | | | On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 30c078de6f3785fe ("pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * pinctrl: sh-pfc: Add SH_PFC_PIN_GROUP_ALIAS()Geert Uytterhoeven2018-03-211-2/+3
| | | | | | | | | | | | | | | | | | | | Add a macro to refer to another pin group with a different name. This will be used to rename wrongly-named pin groups, while retaining backwards compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii groupGeert Uytterhoeven2018-03-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin controller drivers for all R-Car Gen2 SoCs have entries for the EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2. Add the missing pin to restore consistency. Note that technically TX_ER is an optional signal in the MII bus, and thus could have its own group, but this is currently not supported by any R-Car Gen2 pin controller driver. Fixes: 19ef697d1eb7be06 ("sh-pfc: r8a7790: add EtherAVB pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * pinctrl: sh-pfc: r8a77970: Add EtherAVB pin groupsSergei Shtylyov2018-03-141-0/+98
| | | | | | | | | | | | | | Add the EtherAVB pin groups to the R8A77970 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Add R8A77980 PFC supportSergei Shtylyov2018-03-096-0/+2813
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the PFC support for the R8A77980 SoC including pin groups for some on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM, and VIN... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Add PORT_GP_CFG_25() helper macroSergei Shtylyov2018-03-091-2/+6
| | | | | | | | | | | | | | | | | | | | | | They follow the style of the existing PORT_GP_CFG_<n>() macros and will be used by a follow-up patch for the R8A77980 SoC. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77965: Add USB3.0 host pins, groups and functionsTakeshi Kihara2018-03-051-0/+16
| | | | | | | | | | | | | | | | | | This patch adds USB30 (USB3.0 host) pin, group and function to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77965: Add USB2.0 host pins, groups and functionsTakeshi Kihara2018-03-051-0/+32
| | | | | | | | | | | | | | | | | | This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | dt-bindings: pinctrl: Add bindings for Actions S900 SoCManivannan Sadhasivam2018-03-021-0/+178
| | | | | | | | | | | | | | | | Add pinctrl bindings for Actions Semi S900 SoC Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'sh-pfc-for-v4.17-tag1' of ↵Linus Walleij2018-03-0211-50/+4659
|\| | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 - Add DU and VIN pin groups on R-Car D3, - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W, - Add support for the new R-Car M3-N SoC, - Small fixes and cleanups.
| * pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pinsTakeshi Kihara2018-02-281-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most pins on the R8A77965 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Based on a similar patch for the R8A7795 PFC driver by Magnus Damm <damm+renesas@opensource.se>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and functionUlrich Hecht2018-02-261-0/+192
| | | | | | | | | | | | | | | | This patch adds VIN4 pins, groups and function for the R8A77995 (D3) SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functionsUlrich Hecht2018-02-261-0/+454
| | | | | | | | | | | | | | | | This patch adds VIN4 and VIN5 pins, groups and functions for the R8A7795 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functionsUlrich Hecht2018-02-261-0/+454
| | | | | | | | | | | | | | | | This patch adds VIN4 and VIN5 pins, groups and functions for the R8A7796 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functionsJacopo Mondi2018-02-201-0/+110
| | | | | | | | | | | | | | Add EtherAVB groups and functions definitions for R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77965: Add SCIFs groups/functionsJacopo Mondi2018-02-201-0/+296
| | | | | | | | | | | | | | Add SCIF[0-5] groups and pin function definitions for R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Initial R-Car M3-N supportJacopo Mondi2018-02-206-0/+2740
| | | | | | | | | | | | | | | | | | Add initial PFC support for R-Car M3-N (r8a77965) SoC. No groups or functions defined, just pin and registers enumeration. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add TMU pins, groups and functionsTakeshi Kihara2018-02-201-0/+42
| | | | | | | | | | | | | | | | | | | | This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795-es1: Add TMU pins, groups and functionsTakeshi Kihara2018-02-201-0/+42
| | | | | | | | | | | | | | | | | | | | This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A7795 ES1.x SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add TMU pins, groups and functionsTakeshi Kihara2018-02-201-0/+42
| | | | | | | | | | | | | | | | | | | | This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add HDMI pins, groups and functionsTakeshi Kihara2018-02-201-0/+15
| | | | | | | | | | | | | | | | | | This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795-es1: Add HDMI pins, groups and functionsTakeshi Kihara2018-02-201-1/+29
| | | | | | | | | | | | | | | | | | | | | | This patch adds HDMI0 CEC pin, group and function to the R8A7795 ES1.x SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: fixed typo in comment] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and functionsTakeshi Kihara2018-02-201-0/+28
| | | | | | | | | | | | | | | | | | | | This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: fixed typo in comment] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for ↵Takeshi Kihara2018-02-201-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NDFC pins group This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value definition name to SEL_NDFC. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins groupTakeshi Kihara2018-02-201-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment for SSI pins group. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for SSI pins groupTakeshi Kihara2018-02-201-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment for SSI pins group. This is a correction because MOD_SEL register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c8f82 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-02-27 07:19:51 +0000