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* ARM: dts: renesas: Move enable-method to CPU nodesGeert Uytterhoeven2021-05-251-1/+2
| | | | | | | | | | | | | | | | | | | According to Documentation/devicetree/bindings/arm/cpus.yaml, the "enable-method" property should be a property of the individual CPU nodes, and not of the parent "cpus" container node. However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the "cpus" node instead. Secondary CPU bringup and CPU hot (un)plug work regardless, as arm_dt_init_cpu_maps() falls back to looking in the "cpus" node. The cpuidle code does not have such a fallback, so it does not detect the enable-method. Note that cpuidle does not support the "renesas,apmu" enable-method yet, so for now this does not make any difference. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be
* ARM: dts: renesas: Add fck to etheravb-rcar-gen2 clock-names listAdam Ford2021-05-251-0/+1
| | | | | | | | | | The bindings have been updated to support two clocks. Add a clock-names list in the device tree with fck in it. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20210224115146.9131-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* ARM: dts: renesas: Group tuples in APMU cpus propertiesGeert Uytterhoeven2021-03-081-1/+1
| | | | | | | | | To improve human readability and enable automatic validation, the tuples in "cpus" properties in device nodes for Advanced Power Management Units for AP-System Core (APMU) should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210204130517.1647073-2-geert+renesas@glider.be
* ARM: dts: renesas: Fix pin controller node namesGeert Uytterhoeven2020-09-111-1/+1
| | | | | | | | | | According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200821112351.5518-1-geert+renesas@glider.be
* ARM: dts: renesas: Fix SD Card/eMMC interface device node namesYoshihiro Shimoda2020-07-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the device node names as "mmc@". Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree") Fixes: a49f76cddaee ("ARM: dts: r7s9210: Add SDHI support") Fixes: 43304a5f5106 ("ARM: shmobile: r8a73a4: tidyup DT node naming") Fixes: 7d907894bfe3 ("ARM: shmobile: r8a7740: tidyup DT node naming") Fixes: 3ab2ea5fd1ce ("ARM: dts: r8a7742: Add SDHI nodes") Fixes: 63ce8a617b51 ("ARM: dts: r8a7743: Add SDHI controllers") Fixes: b591e323b271 ("ARM: dts: r8a7744: Add SDHI nodes") Fixes: d83010f87ab3 ("ARM: dts: r8a7744: Initial SoC device tree") Fixes: 7079131ef9b9 ("ARM: dts: r8a7745: Add SDHI controllers") Fixes: 0485da788028 ("ARM: dts: r8a77470: Add SDHI1 support") Fixes: 15aa5a95e820 ("ARM: dts: r8a77470: Add SDHI0 support") Fixes: f068cc816015 ("ARM: dts: r8a77470: Add SDHI2 support") Fixes: 14e1d9147d96 ("ARM: shmobile: r8a7778: tidyup DT node naming") Fixes: 2624705ceb7b ("ARM: shmobile: r8a7779: tidyup DT node naming") Fixes: b718aa448378 ("ARM: shmobile: r8a7790: tidyup DT node naming") Fixes: b7ed8a0dd4f1 ("ARM: shmobile: Add SDHI devices to r8a7791 DTSI") Fixes: ce01b14ecf19 ("ARM: dts: r8a7792: add SDHI support") Fixes: fc9ee228f500 ("ARM: dts: r8a7793: Add SDHI controllers") Fixes: b8e8ea127d00 ("ARM: shmobile: r8a7794: add SDHI DT support") Fixes: 33f6be3bf6b7 ("ARM: shmobile: sh73a0: tidyup DT node naming") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1594382936-14114-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* ARM: dts: renesas: Fix IOMMU device node namesYoshihiro Shimoda2020-04-271-6/+6
| | | | | | | | | | | | | | | | Fix IOMMU device node names as "iommu@". Fixes: bbb44da0b595 ("ARM: dts: r8a7743: Add IPMMU DT nodes") Fixes: 0dcba3de5835 ("ARM: dts: r8a7745: Add IPMMU DT nodes") Fixes: 350ae49b97c4 ("ARM: dts: r8a7744: Add IPMMU DT nodes") Fixes: 70496727c082 ("ARM: shmobile: r8a7790: Add IPMMU DT nodes") Fixes: f1951852ed17 ("ARM: shmobile: r8a7791: Add IPMMU DT nodes") Fixes: 098cb3a601e6 ("ARM: shmobile: r8a7793: Add IPMMU nodes") Fixes: 1cb2794f6082 ("ARM: shmobile: r8a7794: Add IPMMU DT nodes") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/1587461756-13317-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* ARM: dts: rzg1: Add reset control properties for displayGeert Uytterhoeven2020-02-241-0/+2
| | | | | | | | | | | | | Add reset control properties to the devices node for the Display Units on all supported RZ/G1 SoCs. Note that on these SoCs, there is only a single reset for all DU channels. Join the clocks lines while at it, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200218133019.22299-3-geert+renesas@glider.be
* ARM: dts: r8a7745: Convert to new DU DT bindingsGeert Uytterhoeven2020-02-241-1/+0
| | | | | | | | | | | The DU DT bindings have been updated to drop the reg-names property. Update the r8a7745 device tree accordingly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20200218132217.21454-1-geert+renesas@glider.be
* ARM: dts: rcar-gen2: Add missing mmio-sram bus propertiesGeert Uytterhoeven2019-12-311-0/+6
| | | | | | | | | | | | | | | | | | "#address-cells", "#size-cells", and "ranges" are required properties for devices nodes compatible with "mmio-sram", leading to warnings when running "make dtbs_check": $ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sram/sram.yaml arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#address-cells' is a required property arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#size-cells' is a required property arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: 'ranges' is a required property ... Fix this by adding the missing properties to the mmio-sram device nodes in the DTS files for all affected R-Car Gen2 and RZ/G1 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191213162604.1890-1-geert+renesas@glider.be
* ARM: dts: rcar-gen2: Fix PCI high address in interrupt-map-maskGeert Uytterhoeven2019-12-311-2/+2
| | | | | | | | | | | | | | | | | | "make dtbs_check" emits warnings like: pci@ee090000: interrupt-map-mask:0:0: 65280 is greater than the maximum of 63488 pci@ee0b0000: interrupt-map-mask:0:0: 65280 is greater than the maximum of 63488 pci@ee0d0000: interrupt-map-mask:0:0: 65280 is greater than the maximum of 63488 According to dt-schemas/schemas/pci/pci-bus.yaml, the PCI high address cell value in the "interrupt-map-mask" property must lie in the range 0..0xf800. Fix this by correcting the values from 0xff00 to 0xf800 in all affected R-Car Gen2 and RZ/G1 DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191213162459.1731-1-geert+renesas@glider.be
* ARM: dts: renesas: Group tuples in interrupt propertiesGeert Uytterhoeven2019-12-201-56/+56
| | | | | | | | | | | | | | | | | | To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. While "make dtbs_check" does not impose this yet for the "interrupts" property, it does for the "interrupt-map" property, leading to warnings like: pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long Fix this by grouping the tuples of the "interrupts" and "interrupt-map" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
* ARM: dts: convert to SPDX identifier for Renesas boardsWolfram Sang2018-07-231-4/+1
| | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add PMU device nodeGeert Uytterhoeven2018-05-141-0/+7
| | | | | | | | | | | | Enable support for the ARM Performance Monitor Units in the Cortex-A7 CPU cores on RZ/G1E by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add watchdog support to SoC dtsiFabrizio Castro2018-04-251-0/+10
| | | | | | | | | | This patch adds watchdog support to the r8a7745 SoC dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Adjust SMP routine sizeFabrizio Castro2018-04-251-1/+1
| | | | | | | | | | | This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add VSP supportBiju Das2018-02-121-0/+18
| | | | | | | | Add VSP support to SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add IPMMU DT nodesBiju Das2018-02-121-0/+58
| | | | | | | | | Add the six IPMMU instances found in the r8a7745 to DT with a disabled status. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: sort subnodes of soc nodeSimon Horman2018-02-121-542/+538
| | | | | | | | | | | | | | Sort the subnodes of the soc node to improve maintainability. The sort key is the address on the bus with instances of the same IP block grouped together and sorted alphabetically. Minor whitespace and line-wrapping changes are also made to match the formatting of R-Car Gen2 SoCs. This patch should not introduce any functional change. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU coreBiju Das2017-12-221-0/+1
| | | | | | | | | Add the missing clock to CA7 CPU1 node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add sound supportBiju Das2017-12-211-0/+180
| | | | | | | | | | | Define the generic r8a7745(RZ/G1E) part of the sound device node. This patch is based on the r8a7794 sound work by Sergei Shtylyov. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add audio DMAC supportBiju Das2017-12-211-0/+31
| | | | | | | | | Instantiate the audio DMA controller on the r8a7745 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add audio clocksBiju Das2017-12-211-0/+21
| | | | | | | | | | Describe the external audio clocks required by the sound driver. Boards that provide audio clocks need to override the clock frequencies. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: move timer node out of busSimon Horman2017-12-201-12/+8
| | | | | | | | | | | | | | | | The timer node does not have any register properties and thus shouldn't be placed on the bus. This problem is flagged by the compiler as follows: $ make dtbs W=1 ... arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property DTC arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* ARM: dts: r8a7745: sort root sub-nodes alphabeticallySimon Horman2017-12-201-24/+24
| | | | | | | | Sort root sub-nodes alphabetically to allow for easier maintenance of this file. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* ARM: dts: r8a7745: Add CMT SoC specific supportFabrizio Castro2017-12-201-0/+32
| | | | | | | | | Add CMT[01] support to SoC DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add TPU supportFabrizio Castro2017-12-201-0/+10
| | | | | | | | | Add TPU support to SoC DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add PWM SoC supportFabrizio Castro2017-12-201-0/+70
| | | | | | | | | Add the definitions for pwm[0123456] to the SoC .dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add APMU node and second CPU coreFabrizio Castro2017-12-071-0/+16
| | | | | | | | | | | Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: add VIN dt supportFabrizio Castro2017-11-271-0/+24
| | | | | | | | Add VIN[01] support to SoC dt. Also, add aliases. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add CAN[01] SoC supportFabrizio Castro2017-11-271-0/+36
| | | | | | | | Add the definitions for can0 and can1 to the SoC .dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add DU supportFabrizio Castro2017-11-271-0/+27
| | | | | | | | | | Add du node to r8a7745 SoC DT. Boards that want to enable the DU need to specify the output topology. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Use R-Car SDHI Gen2 fallback compat stringSimon Horman2017-11-271-3/+6
| | | | | | | | | | Use newly added R-Car SDHI Gen2 fallback compat string in the DT of the r8a7745 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add IIC cores to dtsiFabrizio Castro2017-11-271-0/+36
| | | | | | | | | | Add iic0 and iic1 nodes to SoC dtsi. Also, define aliases i2c6 and i2c7. Board specific DT files will enable the interfaces if needed. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Enable DMA for HSUSBBiju Das2017-11-271-0/+3
| | | | | | | | | | From: Biju Das <biju.das@bp.renesas.com> This patch adds DMA properties to the HSUSB node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add USB-DMAC device nodesBiju Das2017-11-271-0/+28
| | | | | | | | From: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add HS-USB device nodeBiju Das2017-11-271-0/+14
| | | | | | | | | | | From: Biju Das <biju.das@bp.renesas.com> Define the R8A7745 generic part of the HS-USB device node. It is up to the board file to enable the device. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Use R-Car Gen2 Ether fallback compat stringSimon Horman2017-11-271-1/+2
| | | | | | | | | | | Use newly added R-Car Gen2 Ether fallback compat string in the DT of the r8a7745 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* ARM: dts: r8a7745: Link PCI USB devices to USB PHYBiju Das2017-10-121-0/+24
| | | | | | | | | | Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add USB PHY DT supportBiju Das2017-10-121-0/+22
| | | | | | | | | Define the r8a7745 generic part of the USB PHY device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add internal PCI bridge nodesBiju Das2017-10-121-0/+46
| | | | | | | | | Add device nodes for the r8a7745 internal PCI bridge devices. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add MSIOF[012] supportFabrizio Castro2017-09-281-0/+51
| | | | | | | | | | Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Also, define aliases for spi[123]. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add QSPI supportFabrizio Castro2017-09-211-0/+17
| | | | | | | | | Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add SDHI controllersFabrizio Castro2017-09-191-0/+42
| | | | | | | | Add the SDHI controllers to the r8a7745 device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add Ethernet AVB supportBiju Das2017-09-191-0/+13
| | | | | | | Add Ethernet AVB support for r8a7745 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add MMC interface supportFabrizio Castro2017-09-191-0/+16
| | | | | | | Add MMC interface support for r8a7745 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add I2C DT supportFabrizio Castro2017-09-191-0/+93
| | | | | | | Add I2C[0-5] devices to the r8a7745 device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add GPIO supportBiju Das2017-09-191-0/+105
| | | | | | | Describe GPIO blocks in the R8A7745 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: add PFC supportSergei Shtylyov2017-08-151-1/+6
| | | | | | | | Define the generic R8A7745 part of the PFC device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Reserve SRAM for the SMP jump stubGeert Uytterhoeven2017-07-271-0/+8
| | | | | | | Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* ARM: dts: r8a7745: Add Inter Connect RAMGeert Uytterhoeven2017-07-271-0/+15
| | | | | | | RZ/G1E has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit (git 2.34.1) at 2025-02-24 13:26:21 +0000