aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/sama5d2.dtsi
Commit message (Collapse)AuthorAgeFilesLines
* ARM: dts: at91: sama5d2: Name the qspi clockTudor Ambarus2021-12-131-0/+2
| | | | | | | | | | | | Naming clocks is a good practice. The atmel-quadspi driver supports an unnamed clock for the peripheral clock in order to be backward compatible with old DTs, but it is recommended to name the clocks on new DTs. The driver's bindings file requires the clock-names property, so name the clock. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211209102542.254153-1-tudor.ambarus@microchip.com
* ARM: dts: at91: sama5d2/trivial: fix letter case for etm hex addressNicolas Ferre2021-04-121-2/+2
| | | | | | | | | | | | | Fix the etm node hex address to lower case for matching regexp specification and removing the additional warning that looks like: arch/arm/boot/dts/at91-sama5d2_ptc_ek.dt.yaml: /: 'etm@73C000' does not match any of the regexes: '@(0|[1-9a-f][0-9a-f]*)$', '^[^@]+$', 'pinctrl-[0-9]+' Reported-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: at91: sama5d2: add ETB and ETM unit nameNicolas Ferre2021-04-071-2/+2
| | | | | | | | | | | | | | | | Add unit address to the ETB and ETM nodes. It also allow us to get rid of the warnings: ../arch/arm/boot/dts/sama5d2.dtsi:43.6-57.4: Warning (unit_address_vs_reg): /etb: node has a reg or ranges property, but no unit name ../arch/arm/boot/dts/sama5d2.dtsi:59.6-73.4: Warning (unit_address_vs_reg): /etm: node has a reg or ranges property, but no unit name when we compile with W=1. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210402170139.140595-1-nicolas.ferre@microchip.com
* ARM: dts: at91: sama5d2: fix CAN message ram offset and sizeNicolas Ferre2020-12-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | CAN0 and CAN1 instances share the same message ram configured at 0x210000 on sama5d2 Linux systems. According to current configuration of CAN0, we need 0x1c00 bytes so that the CAN1 don't overlap its message ram: 64 x RX FIFO0 elements => 64 x 72 bytes 32 x TXE (TX Event FIFO) elements => 32 x 8 bytes 32 x TXB (TX Buffer) elements => 32 x 72 bytes So a total of 7168 bytes (0x1C00). Fix offset to match this needed size. Make the CAN0 message ram ioremap match exactly this size so that is easily understandable. Adapt CAN1 size accordingly. Fixes: bc6d5d7666b7 ("ARM: dts: at91: sama5d2: add m_can nodes") Reported-by: Dan Sneddon <dan.sneddon@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Cristian Birsan <cristian.birsan@microchip.com> Cc: stable@vger.kernel.org # v4.13+ Link: https://lore.kernel.org/r/20201203091949.9015-1-nicolas.ferre@microchip.com
* ARM: dts: at91: sama5d2: map securam as deviceClaudiu Beznea2020-12-031-0/+1
| | | | | | | | | | | | | Due to strobe signal not being propagated from CPU to securam the securam needs to be mapped as device or strongly ordered memory to work properly. Otherwise, updating to one offset may affect the adjacent locations in securam. Fixes: d4ce5f44d4409 ("ARM: dts: at91: sama5d2: Add securam node") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/1606903025-14197-3-git-send-email-claudiu.beznea@microchip.com
* ARM: dts: at91: sama5d2: add missing flexcom spi node propertiesAlexandre Belloni2020-09-161-0/+10
| | | | | | | | | SPI nodes require #address-cells and #size-cells add those properties in the flexcom spi nodes. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20200831171129.3886857-8-alexandre.belloni@bootlin.com
* ARM: dts: at91: add unit-address to memory nodeAlexandre Belloni2020-09-161-1/+1
| | | | | | | | The memory node requires a unit-address, add it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20200831171129.3886857-7-alexandre.belloni@bootlin.com
* ARM: dts: at91: fix sram nodesAlexandre Belloni2020-09-031-0/+7
| | | | | | | | | The ranges, #address-cells and #size-cells properties are mandatory, add them to the sram nodes. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20200831171129.3886857-4-alexandre.belloni@bootlin.com
* Merge tag 'timers-v5.9' of ↵Thomas Gleixner2020-07-231-6/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clock event/surce driver changes from Daniel Lezcano: - Add sama5d2 support and rework the 32kHz clock handling (Alexandre Belloni) - Add the high resolution support for SMP/SMT on the Ingenic timer (Zhou Yanjie) - Add support for i.MX TPM driver with ARM64 (Anson Huang) - Fix typo by replacing KHz to kHz (Geert Uytterhoeven) - Add 32kHz support by setting the minimum ticks to 5 on Nomadik MTU (Linus Walleij) - Replace HTTP links with HTTPS ones for security reasons (Alexander A. Klimov) - Add support for the Ingenic X1000 OST (Zhou Yanjie)
| * ARM: dts: at91: sama5d2: add TCB GCLKAlexandre Belloni2020-07-111-6/+6
| | | | | | | | | | | | | | | | The sama5d2 tcbs take an extra input clock, their gclk. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200710230813.1005150-4-alexandre.belloni@bootlin.com
* | Merge tag 'usb-5.8-rc1' of ↵Linus Torvalds2020-06-071-120/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY driver updates from Greg KH: "Here are the large set of USB and PHY driver updates for 5.8-rc1. Nothing huge, just lots of little things: - USB gadget fixes and additions all over the place - new PHY drivers - PHY driver fixes and updates - XHCI driver updates - musb driver updates - more USB-serial driver ids added - various USB quirks added - thunderbolt minor updates and fixes - typec updates and additions All of these have been in linux-next for a while with no reported issues" * tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (245 commits) usb: dwc3: meson-g12a: fix USB2 PHY initialization on G12A and A1 SoCs usb: dwc3: meson-g12a: fix error path when fetching the reset line fails Revert "dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings" Revert "dt-bindings: usb: qcom,dwc3: Add compatible for SC7180" Revert "dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver" USB: serial: ch341: fix lockup of devices with limited prescaler USB: serial: ch341: add basis for quirk detection CDC-ACM: heed quirk also in error handling USB: serial: option: add Telit LE910C1-EUX compositions usb: musb: Fix runtime PM imbalance on error usb: musb: jz4740: Prevent lockup when CONFIG_SMP is set usb: musb: mediatek: add reset FADDR to zero in reset interrupt handle usb: musb: use true for 'use_dma' usb: musb: start session in resume for host port usb: musb: return -ESHUTDOWN in urb when three-strikes error happened USB: serial: qcserial: add DW5816e QDL support thunderbolt: Add trivial .shutdown usb: dwc3: keystone: Turn on USB3 PHY before controller dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property dt-bindings: usb: convert keystone-usb.txt to YAML ...
| * | ARM: dts: at91: Remove the USB EP child nodeGregory CLEMENT2020-05-251-120/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The endpoint configuration used to be stored in the device tree, however the configuration depend on the "version" of the controller itself. Then the EP child node are useless and describe as deprecated in the documentation binding: remove all the nodes from the SoC device tree file. Remove also the #address-cells and #size-cells properties that are no longer needed. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* | ARM: dts: at91: sama5d2: Add missing flexcom definitionsTudor Ambarus2020-05-151-0/+79
| | | | | | | | | | | | | | | | Describe all the flexcom functions for all the flexcom nodes. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-13-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Remove i2s and tcb aliases from SoC dtsiTudor Ambarus2020-05-151-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Device aliases are board-specific, if needed one should define them in board dts rather than in the SoC dtsi. If an alias from the SoC dtsi is addressed by a driver that does not use any of the of_alias*() methods, we can drop it. This is the case for the i2s aliases, drop them. tcb aliases point to nodes that are not enabled in any of the sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any board using that alias is already broken, so get rid of the tcb aliases too. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-14-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and I2C flx0 functionsTudor Ambarus2020-05-151-0/+18
| | | | | | | | | | | | | | | | | | | | | | Spare boards of duplicating the DMA bindings. Describe the flx0 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-12-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Add DMA bindings for the flx1 I2C functionTudor Ambarus2020-05-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | Spare boards of duplicating the DMA bindings. Describe the flx1 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-11-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Add DMA bindings for the flx3 SPI functionTudor Ambarus2020-05-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | Spare boards of duplicating the DMA bindings. Describe the flx3 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-10-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and UART flx4 functionsTudor Ambarus2020-05-151-0/+18
| | | | | | | | | | | | | | | | | | | | | | Spare boards of duplicating the DMA bindings. Describe the flx4 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-9-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Specify the FIFO size for the Flexcom UARTTudor Ambarus2020-05-151-0/+2
| | | | | | | | | | | | | | | | | | The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs. Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-8-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsiTudor Ambarus2020-05-151-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. There is a single functional change in this patch. With the move of the flx0 uart5 definition in the SoC dtsi, the uart5 from at91-sama5d27_wlsom1_ek.dts inherits the following optional property: atmel,fifo-size = <32>; This particular change was tested by Codrin. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-7-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsiTudor Ambarus2020-05-151-0/+29
| | | | | | | | | | | | | | | | | | | | The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-6-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsiTudor Ambarus2020-05-151-0/+18
| | | | | | | | | | | | | | | | | | | | The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-5-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Move flx3 definitions in the SoC dtsiTudor Ambarus2020-05-151-0/+29
| | | | | | | | | | | | | | | | | | | | The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-4-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | ARM: dts: at91: sama5d2: Move flx4 definitions in the SoC dtsiTudor Ambarus2020-05-151-0/+40
|/ | | | | | | | | | The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-3-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: use correct rtc compatibleAlexandre Belloni2020-03-091-1/+1
| | | | | | | Use the sama5d2 specific compatible string for the RTC. Link: https://lore.kernel.org/r/20191229204421.337612-8-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: set the sdmmc gclk frequencyLudovic Desroches2019-12-101-0/+4
| | | | | | | | | Set the frequency of the generated clock used by sdmmc devices in order to not rely on the configuration done by previous components. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20191128074522.69706-3-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: mark secumod as a GPIO controllerAndrei Stefanescu2019-12-091-1/+4
| | | | | | | | | | | | | | The Security Module exposes the PIOBU pins which an be used as regular GPIOs. The PIOBU pins are special because they do not lose their voltage during suspend-to-mem. This patch marks the secumod as a GPIO controller. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com> [razvan.stefanescu@microchip.com Updated title] Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-2-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: disable pwm0 by defaultRazvan Stefanescu2019-12-091-0/+1
| | | | | | | | It will be enabled as needed by each board. Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-1-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: add an rtc label for derived boardsKamel Bouhara2019-10-031-1/+1
| | | | | | | | Add an rtc label so we just need to alias it from derived boards. Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com> Link: https://lore.kernel.org/r/20191002145914.14874-1-kamel.bouhara@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: sama5d{2,4}: use SPDX-License-IdentifierAlexandre Belloni2019-04-081-38/+1
| | | | | | | | | | | | | | | External E-Mail The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
* ARM: dts: at91: sama5d2: add labels to soc dtsi for derivative boardsNicolas Ferre2019-03-281-3/+3
| | | | | | | | | This adds labels to commonly used device-tree nodes so that derivative boards can avoid ahb/apb hierarchy. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
* ARM: dts: Kill off skeleton{64}.dtsiRob Herring2019-01-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: at91: sama5d2: switch to new clock bindingAlexandre Belloni2018-11-211-610/+60
| | | | | | Switch sama5d2 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: use the divided clock for SMCRomain Izard2018-11-211-1/+1
| | | | | | | | | | | | | | | | The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock. Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access. Fix the device tree, and the performance of Flash access is improved. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* arm: dts: sama5d2: Update coresight bindings for hardware portsSuzuki K Poulose2018-09-191-7/+10
| | | | | | | | | | Switch to the new coresight bindings for hardware ports Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91/trivial: remove old NAND bindings leftover in sama5d2Nicolas Ferre2018-08-271-38/+0
| | | | | | | | | | As the new bindings are already in place in sama5d2.dtsi and that it's used in the only Mainline board for this product (at91-sama5d2_ptc_ek.dts), we can safely remove the old bindings. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: add nodes for I2S controllersCyrille Pitchen2018-08-271-0/+38
| | | | | | | | | | This patch adds DT nodes for I2S0 and I2S1. It also adds an alias for each I2S node. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [codrin.ciubotariu@microchip.com: removed unnecessary clock phandles] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: add I2S clock muxing nodesCodrin Ciubotariu2018-08-271-0/+18
| | | | | | | | This patch adds two clock muxes for the two I2S buses present on sama5d2 platforms. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: Add resistive touch deviceEugen Hristev2018-08-271-0/+10
| | | | | | | | Add generic resistive touch device which is connected to ADC block inside the SAMA5D2 SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: add channel cells for ADC deviceEugen Hristev2018-08-271-0/+2
| | | | | | | Preparing the ADC device to connect channel consumer drivers Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: dts: at91: sama5d2: TC blocks are also simple-mfd and syscon devicesAlexandre Belloni2017-12-311-2/+6
| | | | | | | | | Add simple-mfd and syscon to the TC blocks to allow to register one of the channels as clocksource properly at boot time and free up the remaining channels for other use. Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
* ARM: dts: at91: sama5d2: added dma property for ADC deviceEugen Hristev2017-12-041-0/+2
| | | | | | | Added DMA property for ADC device Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2017-11-161-6/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM device-tree updates from Arnd Bergmann: "We add device tree files for a couple of additional SoCs in various areas: Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for networking, Amlogic A113D for audio, and Renesas R-Car V3M for automotive. As usual, lots of new boards get added based on those and other SoCs: - Actions S500 based CubieBoard6 single-board computer - Amlogic Meson-AXG A113D based development board - Amlogic S912 based Khadas VIM2 single-board computer - Amlogic S912 based Tronsmart Vega S96 set-top-box - Allwinner H5 based NanoPi NEO Plus2 single-board computer - Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers - Allwinner A83T based TBS A711 Tablet - Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8 - Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500 wireless access points and routers - NXP i.MX51 based Zodiac Inflight Innovations RDU1 board - NXP i.MX53 based GE Healthcare PPD biometric monitor - NXP i.MX6 based Pistachio single-board computer - NXP i.MX6 based Vining-2000 automotive diagnostic interface - NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants - Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone - Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet - Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA - Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board - Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards - Renasas r8a7745 based iWave G22D-SODIMM SoM - Rockchip rk3288 based Amarula Vyasa single-board computer - Samsung Exynos5800 based Odroid HC1 single-board computer For existing SoC support, there was a lot of ongoing work, as usual most of that concentrated on the Renesas, Rockchip, OMAP, i.MX, Amlogic and Allwinner platforms, but others were also active. Rob Herring and many others worked on reducing the number of issues that the latest version of 'dtc' now warns about. Unfortunately there is still a lot left to do. A rework of the ARM foundation model introduced several new files for common variations of the model" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits) arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3 dt-bindings: bus: Add documentation for the Technologic Systems NBUS arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock ARM: dts: owl-s500: Add CubieBoard6 dt-bindings: arm: actions: Add CubieBoard6 ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock ARM: dts: owl-s500: Set power domains for CPU2 and CPU3 arm: dts: mt7623: remove unused compatible string for pio node arm: dts: mt7623: update usb related nodes arm: dts: mt7623: update crypto node ARM: dts: sun8i: a711: Enable USB OTG ARM: dts: sun8i: a711: Add regulator support ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1 ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1 ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes ARM: dts: sunxi: Add dtsi for AXP81x PMIC arm64: dts: allwinner: H5: Restore EMAC changes ...
| * arm: dts: fix unit-address leading 0sRob Herring2017-10-201-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | ARM: dts: at91: sama5d2: add ADC hw trigger edge typeEugen Hristev2017-10-091-0/+1
|/ | | | | | | | | Added ADTRG edge type property as interrupt edge type value Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
* Merge tag 'armsoc-devicetree' of ↵Linus Torvalds2017-09-101-1/+76
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM/arm64 Devicetree updates from Olof Johansson: "As usual, device tree updates is the bulk of our material in this merge window. This time around, 559 patches affecting both 32- and 64-bit platforms. Changes are too many to list individually, but some of the larger ones: New platform/SoC support: - Automotive: + Renesas R-Car D3 (R8A77995) + TI DT76x + MediaTek mt2712e - Communication-oriented: + Qualcomm IPQ8074 + Broadcom Stingray + Marvell Armada 8080 - Set top box: + Uniphier PXs3 Besides some vendor reference boards for the SoC above, there are also several new boards/machines: - TI AM335x Moxa UC-8100-ME-T open platform - TI AM57xx Beaglebone X15 Rev C - Microchip/Atmel sama5d27 SoM1 EK - Broadcom Raspberry Pi Zero W - Gemini-based D-Link DIR-685 router - Freescale i.MX6: + Toradex Apalis module + Apalis and Ixora carrier boards + Engicam GEAM6UL Starter Kit - Freescale i.MX53-based Beckhoff CX9020 Embedded PC - Mediatek mt7623-based BananaPi R2 - Several Allwinner-based single-board computers: + Cubietruck plus + Bananapi M3, M2M and M64 + NanoPi A64 + A64-OLinuXino + Pine64 - Rockchip RK3328 Pine64/Rock64 board support - Rockchip RK3399 boards: + RK3399 Sapphire module on Excavator carrier (RK3399 reference design) + Theobroma Systems RK3399-Q7 SoM - ZTE ZX296718 PCBOX Board" * tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits) ARM: dts: at91: at91sam9g45: add AC97 arm64: dts: marvell: mcbin: enable more networking ports arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node arm64: dts: marvell: add TX interrupts for PPv2.2 arm64: dts: uniphier: add PXs3 SoC support ARM: dts: uniphier: add pinctrl groups of ethernet phy mode ARM: dts: uniphier: fix size of sdctrl nodes ARM: dts: uniphier: add AIDET nodes arm64: dts: uniphier: fix size of sdctrl node arm64: dts: uniphier: add AIDET nodes Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2" arm64: dts: uniphier: add reset controller node of analog amplifier arm64: dts: marvell: add Device Tree files for Armada-8KP arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM dt-bindings: add rk3399-q7 SoM ARM: dts: rockchip: enable usb for rv1108-evb ARM: dts: rockchip: add usb nodes for rv1108 SoCs dt-bindings: update grf-binding for rv1108 SoCs ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers ...
| * ARM: dts: at91: sama5d2: add classd nodesCyrille Pitchen2017-07-261-1/+38
| | | | | | | | | | | | | | | | | | This patch adds nodes for the classd device and its generated clock. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * ARM: dts: at91: sama5d2: add isc nodeSongjun Wu2017-07-171-0/+16
| | | | | | | | | | | | | | | | | | | | | | Add isc node, it conflicts with pdmic and uart3. Signed-off-by: Songjun Wu <songjun.wu@microchip.com> [claudiu.beznea@microchip.com: place isc node after hlcdc node] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
| * ARM: dts: at91: sama5d2: add QSPI nodesCyrille Pitchen2017-07-171-0/+22
| | | | | | | | | | | | | | | | | | | | | | This patch adds DT nodes for sama5d2 QSPI controllers. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [claudiu.beznea@microchip.com: change subject to match the desired prefix] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
* | ARM: dts: at91: sama5d2: fix EBI/NAND controllers declarationLudovic Desroches2017-07-171-5/+5
| | | | | | | | | | | | | | | | | | Fix HSMC interrupt ID, PMECC registers and EBI ones. Fixes: d9c41bf30cf8 ("ARM: dts: at91: Declare EBI/NAND controllers") Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
generated by cgit (git 2.34.1) at 2025-02-24 17:13:53 +0000