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* ARM: l2c: fix register namingRussell King2014-05-301-28/+29
| | | | | | | | | | | | | We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement L2C-310 erratum 752271 in core L2C codeRussell King2014-05-301-1/+17
| | | | | | | | Rather than having SoCs work around L2C erratum themselves, move them into core code. This erratum affects the double linefill feature which needs to be disabled for r3p0 to r3p1-50rel0. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide generic hook to intercept writes to secure registersRussell King2014-05-301-12/+30
| | | | | | | | | | | | | When Linux is running in the non-secure world, any write to a secure L2C register will generate an abort. Platforms normally have to call firmware to work around this. Provide a hook for them to intercept any L2C secure register write. l2c_write_sec() avoids writes to secure registers which are already set to the appropriate value, thus avoiding the overhead of needlessly calling into the secure monitor. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move way size calculation data into l2c_init_dataRussell King2014-05-301-9/+20
| | | | | | | Move the way size calculation data (base of way size) out of the switch statement into the provided initialisation data. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add decode for L2C-220 cache waysRussell King2014-05-301-0/+1
| | | | | | | Rather than assuming these are always 8-way, it can be decoded from the auxillary register in the same manner as L2C-210. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move type string into l2c_init_data structureRussell King2014-05-301-7/+13
| | | | | | | | | | Rather than decoding this from the ID register, store it in the l2c_init_data structure. This simplifies things some more, and allows us to better provide further details as to how we're driving the cache. We print the cache ID value anyway should we need to precisely identify the cache hardware. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: remove obsolete l2x0 ops for non-OF initRussell King2014-05-301-206/+0
| | | | | | | | | | | | | | | | | | | | | | non-OF initialisation has never been used with any cache controller which isn't an ARM cache controller, so we can safely get rid of the old (and buggy) l2x0_*-based operations structure. This is also the last reference to: - l2x0_clean_line() - l2x0_inv_line() - l2x0_flush_line() - l2x0_flush_all() - l2x0_clean_all() - l2x0_inv_all() - l2x0_inv_range() - l2x0_clean_range() - l2x0_flush_range() - l2x0_enable() - l2x0_resume() so kill those functions too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: convert Broadcom L2C-310 to new codeRussell King2014-05-301-16/+11
| | | | | | | | The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later. These require no errata workarounds, and so we can directly call the l2c210 functions from their methods. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add L2C-220 specific handlersRussell King2014-05-301-10/+157
| | | | | | | | | | | | The L2C-220 is different from the L2C-210 and L2C-310 in that every operation is a background operation: this means we have to use spinlocks to protect all operations, and we have to wait for every operation to complete. Should a second operation be attempted while a previous operation is in progress, the response will be an imprecise abort. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementationsRussell King2014-05-301-22/+36
| | | | | | | | Where no errata affect the L2C-310 handlers, they are functionally equivalent to L2C-210. Re-use the L2C-210 handlers for the L2C-310 part. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement L2C-310 erratum 588369 as a method overrideRussell King2014-05-301-0/+69
| | | | | | | | | Implement L2C-310 erratum 588369 by overriding the invalidate range and flush range methods in the outer_cache operations structure. This allows us to sensibly contain the erratum code in one place without affecting other locations/implemetations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement L2C-310 erratum 727915 as a method overrideRussell King2014-05-301-0/+20
| | | | | | | | | Implement L2C-310 erratum 727915 by overriding the flush_all method in the outer_cache operations structure. This allows us to sensibly contain the erratum code in one place without affecting other locations or implementations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add L2C-210 specific handlersRussell King2014-05-301-1/+122
| | | | | | | | | | | Add L2C-210 specific cache operation handlers. These are tailored to the requirements of the L2C-210 cache controller, which doesn't require any workarounds. We avoid using the way operations during normal operation, which means we can avoid locking: the only time we use the way operations are during initialisation, and when disabling the cache. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move pl310_set_debug() into l2c-310 codeRussell King2014-05-301-8/+6
| | | | | | | Move the pl310_set_debug() into the l2c-310 code area, and don't hide it with ifdefs. Rename it to l2c310_set_debug(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: simplify l2x0 unlocking codeRussell King2014-05-301-17/+8
| | | | | | | The l2x0 unlocking code is only called from l2x0_enable() now, so move the logic entirely into that function and simplify it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: clean up save/resume functionsRussell King2014-05-301-57/+52
| | | | | | | | | | Rename the pl310 save/resume functions to have a l2c310 prefix - this is it's official name. Use a local cached copy of the l2x0_base virtual address, and also realise that many of the resume function tails are the same as the enable functions, so make a call to the enable function instead of duplicating that code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OFRussell King2014-05-301-74/+77
| | | | | | | | Add the save/resume code hooks to the non-OF implementations as well. There's no reason for the non-OF implementations to be any different from the OF implementations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: clean up L2 cache initialisation messagesRussell King2014-05-301-3/+4
| | | | | | Make one of them purely "English", and the other purely technical. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement fixups for L2 cache controller quirks/errataRussell King2014-05-301-11/+101
| | | | | | | | | Rather than putting quirk handling in __l2c_init(), move it out to a separate function which individual implementations can specify. This helps to localise the quirks to those implementations which require them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move aurora broadcast setup to enable functionRussell King2014-05-301-13/+15
| | | | | | | | Rather than having this hacked into the OF initialiation function, we can handle this via the enable function instead. While here, clean up that code and comments a little. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: only write the auxiliary control register if requiredRussell King2014-05-301-1/+3
| | | | | | | | Avoid unnecessary writes to the auxiliary control register if the register already contains the required value. This allows us to avoid invoking the platforms secure monitor code unnecessarily. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: write auxctrl register before unlockingRussell King2014-05-301-5/+5
| | | | | | | | We should write the auxillary control register before unlocking: the write may be necessary to enable non-secure access to the lock registers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide enable methodRussell King2014-05-301-18/+62
| | | | | | | | Providing an enable method gives L2 cache controllers a chance to do special handling at enable time. This allows us to remove a hack in l2x0_unlock() for Marvell Aurora L2 caches. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: group implementation specific code togetherRussell King2014-05-301-251/+251
| | | | | | | | | | | | | | | | Back in the mists of time, someone decided that it would be a good idea to group like functions together - so all the save functions in one place, all the resume functions in another, all the OF parsing functions some place else. This makes it difficult to get an overview on what a particular implementation is doing - grouping an implementations specific functions together makes more sense, because you can see what it's doing without the clutter of other implementations. Organise it according to implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move l2c save function to __l2c_init()Russell King2014-05-301-3/+7
| | | | | | | There's no reason this functionality should be specific to DT, so move it into the common initialisation function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: pass iomem address into data->save functionRussell King2014-05-301-16/+16
| | | | | | | Pass the iomem address into this function so we don't have to keep accessing it from a global. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: clean up OF initialisation a bitRussell King2014-05-301-26/+40
| | | | | | | | | | | | | | | | Rather than having a boolean and other tricks to disable some bits of l2x0_init(), split this function into two parts: a common part shared between OF and non-OF, and the non-OF part. The common part can take a block of function pointers, and the cache ID (to cope with Aurora's DT specified ID.) Eliminate the redundant setting of l2x0_base in the OF case, moving it to the non-OF init function. This allows us to localise the OF-specific initialisation handling from the non-OF handling. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add and use L2C revision constantsRussell King2014-05-301-5/+5
| | | | | | | The revision namespace is specific to the L2 cache part, so don't name these with generic identifiers, use a part specific identifier. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: rename cache_wait_way()Russell King2014-05-301-3/+3
| | | | | | | | | | cache_wait_way() is actually used to wait for a particular mask to report clear; it's not really got much to do with cache ways at all. Indeed, it gets used to wait for the C bit to clear on older caches. Rename this with a more generic function name which better reflects its purpose: l2c_wait_mask(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide generic helper for way-based operationsRussell King2014-05-301-6/+9
| | | | | | | | | Provide a generic helper function for way based operations. These are always background operations, and thus have to be waited for before a new operation is commenced. This helper extracts that requirement from several locations in the code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: split out cache unlock codeRussell King2014-05-301-7/+16
| | | | | | | Split the cache unlock code out of l2x0_unlock(). We want to be able to re-use this functionality later. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide generic function for calling set_debug methodRussell King2014-05-301-1/+11
| | | | | | | | Provide a generic function which always calls the set_debug method. This will be used later in the series as some work-arounds require that the debug register be written. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: rename OF specific things, making l2x0_of_data available to allRussell King2014-05-301-32/+32
| | | | | | | | | Rename a few things to help distinguish their function(s): l2x0_of_data -> l2c_init_data setup -> of_parse add of_ prefix to OF specific data Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: tidy up l2x0_of_data declarationsRussell King2014-05-301-16/+14
| | | | | | | Remove NULL initialisers, make these all __initconst structures, and order their members in the same order as the structure declaration. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add helper for L2 cache controller DT IDsRussell King2014-05-301-13/+10
| | | | | | Make it easier to declare L2 cache controller DT IDs by using a macro. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: remove outer_inv_all() methodRussell King2014-05-221-5/+0
| | | | | | | | No one ever calls this function anywhere in the kernel, so let's completely remove it from the outer cache API and turn it into an internal-only thing. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7922/1: l2x0: add Marvell Tauros3 supportSebastian Hesselbarth2013-12-291-8/+40
| | | | | | | | | | | | | This adds support for the Marvell Tauros3 cache controller which is compatible with pl310 cache controller but broadcasts L1 cache operations to L2 cache. While updating the binding documentation, clean up the list of possible compatibles. Also reorder driver compatibles to allow non-ARM derivated to be compatible to ARM cache controller compatibles. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*-. Merge branches 'debug-choice', 'devel-stable' and 'misc' into for-linusRussell King2013-09-051-5/+7
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| | * ARM: 7821/1: DT: binding fixup to align with vendor-prefixes.txtChristian Daudt2013-08-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ this is a follow-up to this discussion: http://archive.arm.linux.org.uk/lurker/message/20130730.230827.a1ceb12a.en.html ] This patchset renames all uses of "bcm," name bindings to "brcm," as they were done prior to knowing that brcm had already been standardized as Broadcom vendor prefix (in Documentation/devicetree/bindings/vendor-prefixes.txt). This will not cause any churn on devices because none of these bindings have made it into production yet. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Christian Daudt <csd@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * ARM: 7820/1: mm: cache-l2x0: Print the cache size in kBFabio Estevam2013-08-201-3/+3
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we have the following output from cache-l2x0: l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1048576 B Using kB for the cache size can improve readability a bit: l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1024 kB While at it use pr_info. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlockWill Deacon2013-08-121-1/+1
|/ | | | | | | writel_relaxed and spin_unlock are both store operations, so we only need to enforce store ordering in the dsb. Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: 7716/1: bcm281xx: Add L2 support for Rev A2 chipsChristian Daudt2013-05-151-0/+158
| | | | | | | | | | | | | | | | | | Rev A2 SoCs have an unorthodox memory re-mapping and this needs to be reflected in the cache operations. This patch adds new outer cache functions for the l2x0 driver to support this SoC revision. It also adds a new compatible value for the cache to enable this functionality. Updates from V1: - remove section 1 altogether and note that in comments - simplify section selection caused by section 1 removal - BUG_ON just in case section 1 shows up Signed-off-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug ↵Rob Herring2013-04-031-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | init Commit b8db6b8 (ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl) moved the masking of the part ID which caused the RTL version to be lost. Commit 6248d06 (ARM: 7545/1: cache-l2x0: make outer_cache_fns a field of l2x0_of_data) changed how .set_debug is initialized. Both commits break commit 74ddcdb (ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier) which uses the RTL version to conditionally set .set_debug function pointer. Commit b8db6b8 also caused the printed cache ID to be missing the version information. Fix this by reverting how the part number is masked so the RTL version info is maintained. The cache-id-part DT property does not set the RTL bits so masking them should have no effect. Also, re-arrange the order of the function pointer init so the .set_debug function can be overridden. Reported-by: Paolo Pisati <paolo.pisati@canonical.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writelGregory CLEMENT2013-01-071-4/+5
| | | | | | | | | | | The use of writel instead of writel_relaxed lead to deadlock in some situation (SMP on Armada 370 for instance). The use of writel_relaxed as it was done in the rest of this driver fixes this bug. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT ↵Gregory CLEMENT2013-01-071-8/+14
| | | | | | | | | | | | | enable This patch fixes a bug for Aurora L2 cache controller when the write-through mode is enable. For the clean operation even if we don't have to flush the lines we still need to invalidate them. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlierRob Herring2013-01-021-1/+2
| | | | | | | | | | | | | | PL310 errata work-arounds using .set_debug function are only needed on r3p0 and earlier, so check the rev and only set .set_debug on older revs. Avoiding debug register accesses fixes aborts on non-secure platforms like highbank. It is assumed that non-secure platforms needing these work-arounds have already implemented .set_debug with secure monitor calls. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrlGregory CLEMENT2012-11-061-13/+210
| | | | | | | | | | | | | | | | | | | | | | Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as: - no cache id part number available through hardware (need to get it by the DT). - always write through mode available. - two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). - in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line. Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7545/1: cache-l2x0: make outer_cache_fns a field of l2x0_of_dataGregory CLEMENT2012-10-181-15/+40
| | | | | | | | | | | | | | Instead of having multiple functions belonging to outer_cache and filling this structure on the fly, use a outer_cache_fns field inside l2x0_of_data and just memcopy it into outer_cache depending of the type of the l2x0 cache. For non DT case, the former code was kept. [rmk: fixed a style issue] Tested-and-Reviewed-by: Yehuda Yitschak <yehuday@marvell.com> Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2012-10-071-2/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: "This is the first chunk of ARM updates for this merge window. Conflicts are expected in two files - asm/timex.h and mach-integrator/integrator_cp.c. Nothing particularly stands out more than anything else. Most of the growth is down to the opcodes stuff from Dave Martin, which is countered by Rob's patches to use more of the asm-generic headers on ARM." (A few more conflicts grew since then, but it all looked fairly trivial) * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (44 commits) ARM: 7548/1: include linux/sched.h in syscall.h ARM: 7541/1: Add ARM ERRATA 775420 workaround ARM: ensure vm_struct has its phys_addr member filled in ARM: 7540/1: kexec: Check segment memory addresses ARM: 7539/1: kexec: scan for dtb magic in segments ARM: 7538/1: delay: add registration mechanism for delay timer sources ARM: 7536/1: smp: Formalize an IPI for wakeup ARM: 7525/1: ptrace: use updated syscall number for syscall auditing ARM: 7524/1: support syscall tracing ARM: 7519/1: integrator: convert platform devices to Device Tree ARM: 7518/1: integrator: convert AMBA devices to device tree ARM: 7517/1: integrator: initial device tree support ARM: 7516/1: plat-versatile: add DT support to FPGA IRQ ARM: 7515/1: integrator: check PL010 base address from resource ARM: 7514/1: integrator: call common init function from machine ARM: 7522/1: arch_timers: register a time/cycle counter ARM: 7523/1: arch_timers: enable the use of the virtual timer ARM: 7531/1: mark kernelmode mem{cpy,set} non-experimental ARM: 7520/1: Build dtb files in all target ARM: Fix build warning in arch/arm/mm/alignment.c ...
| * ARM: 7507/1: cache-l2x0.c: save the final aux ctrl value for resumingYilu Mao2012-09-151-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a bug if l2x0 controller has been enabled when calling l2x0_init, the aux ctrl register will not be saved in l2x0_saved_regs. Therefore we will use uninitialized l2x0_saved_regs.aux_ctrl for resuming later. In this patch, the aux ctrl value is read and saved after it is initialized. So we have the real value being set for resuming. Link: http://lkml.kernel.org/r/1336046857-24133-1-git-send-email-ylmao@marvell.com Signed-off-by: Yilu Mao <ylmao@marvell.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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