| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: meson: split divider and gate part of mpll | Jerome Brunet | 2018-03-13 | 1 | -44/+0 |
| * | clk: meson: migrate mplls clocks to clk_regmap | Jerome Brunet | 2018-03-13 | 1 | -65/+37 |
| * | clk: meson: add axg misc bit to the mpll driver | Jerome Brunet | 2018-02-12 | 1 | -0/+7 |
| * | clk: meson: mpll: use 64-bit maths in params_from_rate | Martin Blumenstingl | 2017-12-23 | 1 | -1/+1 |
| * | clk: meson: mpll: fix mpll0 fractional part ignored | Jerome Brunet | 2017-08-01 | 1 | -0/+7 |
| * | clk: meson: mpll: use 64bit math in rate_from_params | Martin Blumenstingl | 2017-04-07 | 1 | -1/+1 |
| * | clk: meson: mpll: fix division by zero in rate_from_params | Martin Blumenstingl | 2017-04-07 | 1 | -11/+15 |
| * | clk: meson: mpll: correct N2 maximum value | Jerome Brunet | 2017-03-27 | 1 | -1/+1 |
| * | clk: meson: mpll: add rw operation | Jerome Brunet | 2017-03-27 | 1 | -5/+147 |
| * | clk: meson: add mpll support | Michael Turquette | 2016-06-22 | 1 | -0/+94 |
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