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path: root/drivers/clk/renesas
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* | clk: renesas: r9a07g044: Add M3 Clock supportBiju Das2022-05-051-1/+4
* | clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das2022-05-051-1/+4
* | clk: renesas: r9a07g044: Add M1 clock supportBiju Das2022-05-051-1/+10
* | clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2022-05-052-0/+136
* | clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2022-05-052-0/+103
* | clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2022-05-052-0/+235
* | clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda2022-04-295-0/+231
* | clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda2022-04-294-16/+24
* | clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das2022-04-281-0/+10
* | clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das2022-04-281-0/+9
* | clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das2022-04-281-0/+5
* | clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das2022-04-281-0/+12
* | clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das2022-04-281-0/+20
* | clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das2022-04-281-0/+12
* | clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal2022-04-281-1/+1
* | clk: renesas: r8a779f0: Add UFS clockYoshihiro Shimoda2022-04-251-0/+1
* | clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das2022-04-131-0/+35
* | clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das2022-04-131-0/+10
* | clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das2022-04-131-0/+13
* | clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das2022-04-131-0/+5
* | clk: renesas: Add support for RZ/G2UL SoCBiju Das2022-04-135-1/+171
* | clk: renesas: Move RPC core clocksGeert Uytterhoeven2022-04-1312-57/+51
* | clk: renesas: rzg2l: Simplify multiplication/shift logicGeert Uytterhoeven2022-04-131-1/+1
* | clk: renesas: r8a77995: Add RPC clocksGeert Uytterhoeven2022-04-112-1/+13
* | clk: renesas: r8a77990: Add RPC clocksGeert Uytterhoeven2022-04-111-0/+9
* | clk: renesas: rzg2l: Remove unused notifiersPhil Edworthy2022-04-041-2/+0
|/
* clk: renesas: r8a779f0: Add PFC clockGeert Uytterhoeven2022-02-221-0/+1
* clk: renesas: r8a779f0: Add I2C clocksGeert Uytterhoeven2022-02-221-0/+6
* clk: renesas: r8a779f0: Add WDT clockGeert Uytterhoeven2022-02-221-0/+9
* clk: renesas: r8a779f0: Fix RSW2 clock dividerGeert Uytterhoeven2022-02-221-1/+1
* clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-105-191/+250
* clk: renesas: r8a779a0: Add CANFD module clockUlrich Hecht2022-01-241-0/+1
* clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3Lad Prabhakar2022-01-241-2/+2
* clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko2022-01-242-0/+2
* clk: renesas: r8a779f0: Add SYS-DMAC clocksYoshihiro Shimoda2022-01-241-0/+2
* clk: renesas: r9a07g044: Add GPU clock and reset entriesBiju Das2021-12-081-0/+9
* clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das2021-12-082-0/+10
* clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macroBiju Das2021-12-081-2/+2
* clk: renesas: cpg-mssr: Add support for R-Car S4-8Yoshihiro Shimoda2021-12-085-0/+196
* clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverYoshihiro Shimoda2021-12-087-341/+437
* clk: renesas: r9a07g044: Add TSU clock and reset entryBiju Das2021-11-261-0/+3
* clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()Lad Prabhakar2021-11-191-2/+1
* clk: renesas: cpg-mssr: Check return value of pm_genpd_init()Lad Prabhakar2021-11-191-1/+14
* clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()Lad Prabhakar2021-11-191-2/+1
* clk: renesas: rzg2l: Check return value of pm_genpd_init()Lad Prabhakar2021-11-191-1/+13
* clk: renesas: r9a07g044: Add RSPI clock and reset entriesLad Prabhakar2021-11-191-0/+9
* clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIVBiju Das2021-11-191-1/+10
* clk: renesas: rzg2l: Add CPG_PL1_DDIV macroBiju Das2021-11-191-0/+2
* clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRSTWolfram Sang2021-11-191-12/+3
* clk: renesas: rcar-gen3: Switch to new SD clock handlingWolfram Sang2021-11-194-202/+32
generated by cgit (git 2.34.1) at 2025-02-24 00:13:44 +0000