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* drm/msm: clarify downstream bus scalingRob Clark2015-06-113-4/+4
| | | | | | | | | | A few spots in the driver have support for downstream android CONFIG_MSM_BUS_SCALING. This is mainly to simplify backporting the driver for various devices which do not have sufficient upstream kernel support. But the intentionally dead code seems to cause some confusion. Rename the #define to make this more clear. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-06-115-58/+573
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: dump scratch regs and other info on hangRob Clark2015-06-114-3/+25
| | | | | | | | | | | | | | Dump a bit more info when the GPU hangs, without having hang_debug enabled (which dumps a *lot* of registers). Also dump the scratch registers, as they are useful for determining where in the cmdstream the GPU hung (and they seem always safe to read when GPU has hung). Note that the freedreno gallium driver emits increasing counter values to SCRATCH6 (to identify tile #) and SCRATCH7 (to identify draw #), so these two in particular can be used to "triangulate" where in the cmdstream the GPU hung. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix locking inconsistencies in gpu->destroy()Rob Clark2015-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In error paths, this was being called without struct_mutex held. Leading to panics like: msm 1a00000.qcom,mdss_mdp: No memory protection without IOMMU Kernel panic - not syncing: BUG! CPU: 0 PID: 1409 Comm: cat Not tainted 4.0.0-dirty #4 Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) Call trace: [<ffffffc000089c78>] dump_backtrace+0x0/0x118 [<ffffffc000089da0>] show_stack+0x10/0x20 [<ffffffc0006686d4>] dump_stack+0x84/0xc4 [<ffffffc0006678b4>] panic+0xd0/0x210 [<ffffffc0003e1ce4>] drm_gem_object_free+0x5c/0x60 [<ffffffc000402870>] adreno_gpu_cleanup+0x60/0x80 [<ffffffc0004035a0>] a3xx_destroy+0x20/0x70 [<ffffffc0004036f4>] a3xx_gpu_init+0x84/0x108 [<ffffffc0004018b8>] adreno_load_gpu+0x58/0x190 [<ffffffc000419dac>] msm_open+0x74/0x88 [<ffffffc0003e0a48>] drm_open+0x168/0x400 [<ffffffc0003e7210>] drm_stub_open+0xa8/0x118 [<ffffffc0001a0e84>] chrdev_open+0x94/0x198 [<ffffffc000199f88>] do_dentry_open+0x208/0x310 [<ffffffc00019a4c4>] vfs_open+0x44/0x50 [<ffffffc0001aa26c>] do_last.isra.14+0x2c4/0xc10 [<ffffffc0001aac38>] path_openat+0x80/0x5e8 [<ffffffc0001ac354>] do_filp_open+0x2c/0x98 [<ffffffc00019b60c>] do_sys_open+0x13c/0x228 [<ffffffc00019b72c>] SyS_openat+0xc/0x18 CPU1: stopping But there isn't any particularly good reason to hold struct_mutex for teardown, so just standardize on calling it without the mutex held and use the _unlocked() versions for GEM obj unref'ing Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-02-015-265/+456
| | | | | | | | | | Resync from rnndb database, to pull in register defines for: * eDP * HDMI/HDCP * mdp4/mdp5 YUV support * mdp5 hw cursor support Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Deletion of unnecessary checks before the function call ↵Markus Elfring2014-12-171-4/+2
| | | | | | | | | | | | | "release_firmware" The release_firmware() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: a4xx support for msm-drmAravind Ganesan2014-11-165-1/+662
| | | | | | | Added a4xx GPU support. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Handle register offset differences between a3xx and a4xxAravind Ganesan2014-11-163-6/+218
| | | | | | | | | | | | Register offsets have changed between a3xx and a4xx GPUs. To be able access these registers in common code, we create a lookup table, and set of read-write APIs to access the register through the lookup table. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> [robclark: remove REG_ADRENO_UNDEFINED, just use zero, and minor tweaks for latest generated headers] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2014-11-165-79/+2430
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: slight init order cleanupRob Clark2014-11-161-6/+6
| | | | | | | | | Move anything that can fail after call to base class msm_gpu_init(). This way, if we fail, active_list has already been initialized so we don't trip 'WARN_ON(!list_empty(&gpu->active_list))' in msm_gpu_cleanup(). Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: push dump/show stuff to base classRob Clark2014-09-103-35/+39
| | | | | | | | | Add ptr to list of interesting registers to 'struct adreno_gpu' and use that to move most of the debugfs show and register dump bits down into adreno_gpu. This will avoid duplication as support for additional adreno generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: bit of init refactoringRob Clark2014-09-104-41/+40
| | | | | | | Push a few bits down into adreno_gpu so they won't have to be duplicated as support for additional adreno generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: move decision about what gpu to to loadRob Clark2014-09-103-69/+125
| | | | | | | Move this into into adreno_device, and decide based on gpu revision rather than just assuming a3xx. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: split adreno device out into it's own fileRob Clark2014-09-102-155/+169
| | | | | | | We'd rather not duplicate these parts as support for additional gpu generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2014-09-104-15/+19
| | | | | | | In particular, pick up the definitions for a handful of LVDS related registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix potential deadlock in gpu initRob Clark2014-08-041-3/+5
| | | | | | | | | | | | | Somewhere along the way, the firmware loader sprouted another lock dependency, resulting in possible deadlock scenario: &dev->struct_mutex --> &sb->s_type->i_mutex_key#2 --> &mm->mmap_sem which is problematic vs things like gem mmap. So introduce a separate mutex to synchronize gpu init. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: use upstream iommuRob Clark2014-08-041-0/+8
| | | | | | | | | | | | | | | | | Downstream kernel IOMMU had a non-standard way of dealing with multiple devices and multiple ports/contexts. We don't need that on upstream kernel, so rip out the crazy. Note that we have to move the pinning of the ringbuffer to after the IOMMU is attached. No idea how that managed to work properly on the downstream kernel. For now, I am leaving the IOMMU port name stuff in place, to simplify things for folks trying to backport latest drm/msm to device kernels. Once we no longer have to care about pre-DT kernels, we can drop this and instead backport upstream IOMMU driver. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2014-08-045-80/+574
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: DT support for 8960/8064 (v3)Rob Clark2014-08-041-0/+2
| | | | | | | | | | Now that we (almost) have enough dependencies in place (MMCC, RPM, etc), add necessary DT support so that we can use drm/msm on upstream kernel. v2: update for review comments v3: rebase on component helper changes Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix double struct_mutex acquireRob Clark2014-08-041-5/+0
| | | | | | | Mutex is already grabbed in show_locked().. somehow this slipped through. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add perf logging debugfsRob Clark2014-06-021-5/+15
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: use componentised device supportRob Clark2014-03-311-15/+34
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add chip-id paramRob Clark2014-03-311-0/+6
| | | | | | | | Some of the w/a or different behavior of userspace blob driver seem to be keyed to gpu patch revision, rather than gpu-id. So expose the full chip-id to userspace so it can DTRT. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: crank down gpu when inactiveRob Clark2014-03-311-0/+10
| | | | | | | Shut down the clks when the gpu has nothing to do. A short inactivity timer is used to provide a low pass filter for power transitions. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: spin helperRob Clark2014-03-313-38/+32
| | | | | | | Helper macro to simplify places where we need to poll with timeout waiting for gpu. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add hang_debug module paramRob Clark2014-03-313-1/+52
| | | | | | | msm.hang_debug=y will dump out current register values if the gpu locks up, for easier debugging. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add a330/apq8x74Rob Clark2014-01-094-22/+143
| | | | | | | | | | | | | | | | Add support for adreno 330. Not too much different, just a few differences in initial configuration plus setting OCMEM base. Userspace support is already in upstream mesa. Note that the existing DT code is simply using the bindings from downstream android kernel, to simplify porting of this driver to existing devices. These do not constitute any committed/stable DT ABI. The addition of proper DT bindings will be a subsequent patch, at which point (as best as possible) I will try to support either upstream bindings or what is found in downstream android kernel, so that existing device DT files can be used. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: resync generated headersRob Clark2014-01-094-161/+281
| | | | | | resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add support for msm8060ab/bstemRob Clark2014-01-091-3/+13
| | | | | | | This adds the necessary configuration for the APQ8060A SoC (dual-core krait + a320 gpu) as found on the bstem board. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add support for non-IOMMU systemsRob Clark2014-01-092-5/+23
| | | | | | | | | | | | | | | | | | | | | | Add a VRAM carveout that is used for systems which do not have an IOMMU. The VRAM carveout uses CMA. The arch code must setup a CMA pool for the device (preferrably in highmem.. a 256m-512m VRAM pool in lowmem is not cool). The user can configure the VRAM pool size using msm.vram module param. Technically, the abstraction of IOMMU behind msm_mmu is not strictly needed, but it simplifies the GEM code a bit, and will be useful later when I add support for a2xx devices with GPUMMU, so I decided to keep this part. It appears to be possible to configure the GPU to restrict access to addresses within the VRAM pool, but this is not done yet. So for now the GPU will refuse to load if there is no sort of mmu. Once address based limits are supported and tested to confirm that we aren't giving the GPU access to arbitrary memory, this restriction can be lifted Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix bus scalingRob Clark2014-01-092-0/+14
| | | | | | | This got a bit broken with original patches when re-arranging things to move dependencies on mach-msm inside #ifndef OF. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add missing MODULE_FIRMWARE()sRob Clark2014-01-091-0/+5
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: resync generated headersRob Clark2013-11-014-27/+81
| | | | | | | resync to latest envytools db, fixes a typo: s/mpd4/mdp4/ Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: David Brown <davidb@codeaurora.org>
* drm/msm: hangcheck harderRob Clark2013-09-101-1/+9
| | | | | | | | | | | | | | If gpu locks up with the rptr shortly beyond the wrap-around point in the ringbuffer, because the rptr was not reset (but wptr is, by virtue of resetting rb->cur), we could end up in a scenario where we think there is not enough space in the ringbuffer for the next cmds. And since the CP won't reset rptr until after processing an IB, this leaves things in a sort of deadlock. So reset rptr too. And a bit more spiffing up of hangcheck to make things easier to debug. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add basic hangcheck/recovery mechanismRob Clark2013-08-243-5/+25
| | | | | | | | | | A basic, no-frills recovery mechanism in case the gpu gets wedged. We could try to be a bit more fancy and restart the next submit after the one that got wedged, but for now keep it simple. This is enough to recover things if, for example, the gpu hangs mid way through a piglit run. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add a3xx gpu supportRob Clark2013-08-244-0/+1023
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for a3xx 3d core. So far, with hardware that I've seen to date, we can have: + zero, one, or two z180 2d cores + a3xx or a2xx 3d core, which share a common CP (the firmware for the CP seems to implement some different PM4 packet types but the basics of cmdstream submission are the same) Which means that the eventual complete "class" hierarchy, once support for all past and present hw is in place, becomes: + msm_gpu + adreno_gpu + a3xx_gpu + a2xx_gpu + z180_gpu This commit splits out the parts that will eventually be common between a2xx/a3xx into adreno_gpu, and the parts that are even common to z180 into msm_gpu. Note that there is no cmdstream validation required. All memory access from the GPU is via IOMMU/MMU. So as long as you don't map silly things to the GPU, there isn't much damage that the GPU can do. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add register definitions for gpuRob Clark2013-08-244-0/+4317
Generated from rnndb files in: https://github.com/freedreno/envytools Keep this split out as a separate commit to make it easier to review the actual driver. Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit (git 2.34.1) at 2025-03-04 17:18:44 +0000