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path: root/drivers/gpu/drm/nouveau/include
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* drm/nouveau/gr/ga102: initial supportBen Skeggs2022-11-093-0/+11
* drm/nouveau/ltc/ga102: initial supportBen Skeggs2022-11-091-1/+2
* drm/nouveau/acr/ga102: initial supportBen Skeggs2022-11-098-0/+197
* drm/nouveau/fb/ga102: load and boot VPR scrubber FWBen Skeggs2022-11-094-0/+60
* drm/nouveau/fifo: expose function to read engine ctxsw statusBen Skeggs2022-11-091-0/+1
* drm/nouveau/ltc: split color vs depth/stencil zbc countsBen Skeggs2022-11-091-6/+9
* drm/nouveau/engine: add HAL for engine-specific rc reset procedureBen Skeggs2022-11-091-0/+2
* drm/nouveau/sec2: dump tracepc info on haltBen Skeggs2022-11-091-0/+1
* drm/nouveau/acr: use common falcon HS FW code for ACR FWsBen Skeggs2022-11-094-27/+37
* drm/nouveau/fb/gp102-: unlock VPR right after devinitBen Skeggs2022-11-091-0/+2
* drm/nouveau/fb: handle sysmem flush page from common codeBen Skeggs2022-11-091-0/+5
* drm/nouveau/flcn: new code to load+boot simple HS FWs (VPR scrubber)Ben Skeggs2022-11-093-1/+115
* drm/nouveau/flcn: rework falcon resetBen Skeggs2022-11-092-9/+13
* drm/nouveau/sec2: unload RTOS before tearing down WPRBen Skeggs2022-11-094-2/+9
* drm/nouveau/pmu/gm20b,gp10b: boot RTOS from PMU initBen Skeggs2022-11-092-4/+5
* drm/nouveau/gsp: add funcsBen Skeggs2022-11-092-2/+4
* drm/nouveau/fifo/ga100-: initial supportBen Skeggs2022-11-092-0/+3
* drm/nouveau/ce/ga100-: initial supportBen Skeggs2022-11-092-0/+3
* drm/nouveau/fifo: add new channel classesBen Skeggs2022-11-0912-129/+64
* drm/nouveau/fifo: add new engine context handlingBen Skeggs2022-11-091-9/+0
* drm/nouveau/fifo: add RAMFC info to nvkm_chan_funcBen Skeggs2022-11-091-0/+7
* drm/nouveau/fifo: add USERD info to nvkm_chan_funcBen Skeggs2022-11-091-2/+10
* drm/nouveau/fifo: add RAMIN info to nvkm_chan_funcBen Skeggs2022-11-091-2/+2
* drm/nouveau/fifo: add common runlist controlBen Skeggs2022-11-091-1/+1
* drm/nouveau/fifo: add chan start()/stop()Ben Skeggs2022-11-091-3/+4
* drm/nouveau/fifo: add runlist wait()Ben Skeggs2022-11-091-0/+4
* drm/nouveau/fifo: add new engine context trackingBen Skeggs2022-11-091-1/+2
* drm/nouveau/fifo: add new channel lookup interfacesBen Skeggs2022-11-092-8/+5
* drm/nouveau/fifo: tidy up non-stall intr handlingBen Skeggs2022-11-091-2/+5
* drm/nouveau/fifo: use runlist engine info to lookup engine classesBen Skeggs2022-11-091-1/+0
* drm/nouveau/fifo: add cgrp, have all channels be part of oneBen Skeggs2022-11-091-3/+4
* drm/nouveau/fifo: expose per-runlist CHID informationBen Skeggs2022-11-091-1/+3
* drm/nouveau/fifo: add common runlist/engine topologyBen Skeggs2022-11-092-0/+17
* drm/nouveau/fifo: add runqBen Skeggs2022-11-091-0/+2
* drm/nouveau/fifo: add chid allocatorBen Skeggs2022-11-091-0/+3
* drm/nouveau/fifo: unify handling of channel classesBen Skeggs2022-11-093-2/+10
* drm/nouveau/fifo: add chid_nr()Ben Skeggs2022-11-092-2/+1
* drm/nouveau/imem: allow bar2 mapping of user allocationsBen Skeggs2022-11-092-1/+3
* drm/nouveau/flcn: show falcon user in debug outputBen Skeggs2022-11-092-12/+19
* drm/nouveau/nvkm: add locking to subdev/engine init pathsBen Skeggs2022-11-092-9/+22
* drm/nouveau/mc: implement intr handling on top of nvkm_intrBen Skeggs2022-11-091-4/+2
* drm/nouveau/fault/tu102: switch to explicit intr handlersBen Skeggs2022-11-091-0/+2
* drm/nouveau/vfn/tu102-: support new-style interrupt treeBen Skeggs2022-11-091-0/+2
* drm/nouveau/vfn: move NV_USERMODE class from hostBen Skeggs2022-11-092-0/+5
* drm/nouveau/vfn: add stub subdev for dev_funcBen Skeggs2022-11-092-0/+19
* drm/nouveau/intr: add nvkm_subdev_intr() compatibilityBen Skeggs2022-11-093-0/+4
* drm/nouveau/intr: support multiple trees, and explicit interfacesBen Skeggs2022-11-092-0/+62
* drm/nouveau/intr: add shared interrupt plumbing between pci/tegraBen Skeggs2022-11-094-2/+22
* drm/nouveau/top: parse device topology right after devinitBen Skeggs2022-11-091-0/+1
* drm/nouveau/nvkm: give each nvkm_event its own lockdep classBen Skeggs2022-11-091-2/+17
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