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path: root/drivers/gpu/drm/nouveau
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* | drm/nouveau/flcn: new code to load+boot simple HS FWs (VPR scrubber)Ben Skeggs2022-11-0910-66/+594
* | drm/nouveau/flcn: rework falcon resetBen Skeggs2022-11-0916-143/+185
* | drm/nouveau/sec2: switch to newer style interrupt handlerBen Skeggs2022-11-094-13/+26
* | drm/nouveau/sec2: unload RTOS before tearing down WPRBen Skeggs2022-11-0911-51/+91
* | drm/nouveau/pmu/gm20b,gp10b: boot RTOS from PMU initBen Skeggs2022-11-099-60/+92
* | drm/nouveau/pmu: move init() falcon reset to non-nvfw codeBen Skeggs2022-11-098-70/+27
* | drm/nouveau/pmu: move preinit() falcon reset to devinitBen Skeggs2022-11-092-13/+7
* | drm/nouveau/gsp: add funcsBen Skeggs2022-11-095-7/+20
* | drm/nouveau/fifo/ga100-: initial supportBen Skeggs2022-11-0913-276/+610
* | drm/nouveau/ce/ga100-: initial supportBen Skeggs2022-11-098-0/+144
* | drm/nouveau/fifo: add new channel classesBen Skeggs2022-11-0963-1763/+524
* | drm/nouveau/fifo: add new engine object handlingBen Skeggs2022-11-0922-228/+94
* | drm/nouveau/fifo: add new engine context handlingBen Skeggs2022-11-0939-930/+382
* | drm/nouveau/fifo: add RAMFC info to nvkm_chan_funcBen Skeggs2022-11-0929-321/+488
* | drm/nouveau/fifo: add USERD info to nvkm_chan_funcBen Skeggs2022-11-0923-115/+157
* | drm/nouveau/fifo: add RAMIN info to nvkm_chan_funcBen Skeggs2022-11-0916-20/+64
* | drm/nouveau/fifo: add common runlist controlBen Skeggs2022-11-0935-505/+284
* | drm/nouveau/fifo: add common channel recoveryBen Skeggs2022-11-0919-605/+559
* | drm/nouveau/fifo: kill channel on NV_PPBDMA_INTR_1_CTXNOTVALIDBen Skeggs2022-11-093-0/+30
* | drm/nouveau/fifo: kill channel on a selection of PBDMA errorsBen Skeggs2022-11-091-3/+3
* | drm/nouveau/fifo: add chan/cgrp preempt()Ben Skeggs2022-11-0919-86/+102
* | drm/nouveau/fifo: add chan start()/stop()Ben Skeggs2022-11-0927-108/+191
* | drm/nouveau/fifo: add chan bind()/unbind()Ben Skeggs2022-11-0917-37/+115
* | drm/nouveau/fifo: add runlist block()/allow()Ben Skeggs2022-11-0913-14/+95
* | drm/nouveau/fifo: add runlist wait()Ben Skeggs2022-11-0915-32/+102
* | drm/nouveau/fifo: add new engine context trackingBen Skeggs2022-11-097-10/+296
* | drm/nouveau/fifo: add new channel lookup interfacesBen Skeggs2022-11-0928-132/+166
* | drm/nouveau/fifo: merge mmu fault handlers togetherBen Skeggs2022-11-0914-335/+183
* | drm/nouveau/fifo: move PBDMA intr to runqBen Skeggs2022-11-098-102/+84
* | drm/nouveau/fifo: move PBDMA init to runqBen Skeggs2022-11-0915-74/+36
* | drm/nouveau/fifo: program NV_PFIFO_FB_TIMEOUT on initBen Skeggs2022-11-092-0/+2
* | drm/nouveau/fifo: tidy global PBDMA initBen Skeggs2022-11-0914-32/+52
* | drm/nouveau/fifo: tidy up non-stall intr handlingBen Skeggs2022-11-0920-118/+93
* | drm/nouveau/fifo: use explicit intr interfacesBen Skeggs2022-11-0917-89/+105
* | drm/nouveau/fifo: use runlist engine info to lookup engine classesBen Skeggs2022-11-0922-146/+35
* | drm/nouveau/fifo: add cgrp, have all channels be part of oneBen Skeggs2022-11-0913-18/+231
* | drm/nouveau/fifo: expose per-runlist CHID informationBen Skeggs2022-11-098-21/+80
* | drm/nouveau/fifo: expose runlist topology info on all chipsetsBen Skeggs2022-11-0917-116/+81
* | drm/nouveau/fifo: add common runlist/engine topologyBen Skeggs2022-11-0926-43/+583
* | drm/nouveau/fifo: add runqBen Skeggs2022-11-0917-27/+153
* | drm/nouveau/fifo: add chid allocatorBen Skeggs2022-11-0926-21/+209
* | drm/nouveau/fifo: merge gk104_fifo_func into nvkm_host_funcBen Skeggs2022-11-0914-111/+219
* | drm/nouveau/fifo: pre-move some blocks of code aroundBen Skeggs2022-11-096-400/+400
* | drm/nouveau/fifo: unify handling of channel classesBen Skeggs2022-11-0936-191/+410
* | drm/nouveau/fifo: add chid_nr()Ben Skeggs2022-11-0925-137/+114
* | drm/nouveau/imem: allow bar2 mapping of user allocationsBen Skeggs2022-11-096-6/+46
* | drm/nouveau/flcn: show falcon user in debug outputBen Skeggs2022-11-093-16/+22
* | drm/nouveau/nvkm: add locking to subdev/engine init pathsBen Skeggs2022-11-094-69/+142
* | drm/nouveau/mc/ga100: switch to using NV_PMC_DEVICE_ENABLEBen Skeggs2022-11-091-3/+44
* | drm/nouveau/mc: move NV_PMC_ENABLE bashing to chipset-specific codeBen Skeggs2022-11-0916-11/+56
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