aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau
Commit message (Collapse)AuthorAgeFilesLines
...
* | drm/nouveau/gr/gf100-: move some code around to make next commits nicerBen Skeggs2022-11-091-52/+52
| | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: expose function to read engine ctxsw statusBen Skeggs2022-11-093-1/+18
| | | | | | | | | | | | | | Needed to support Ampere differences in gr/gf100-: Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/ltc: split color vs depth/stencil zbc countsBen Skeggs2022-11-0913-27/+42
| | | | | | | | | | | | | | These differ on Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/engine: add HAL for engine-specific rc reset procedureBen Skeggs2022-11-093-2/+14
| | | | | | | | | | | | | | Will be used to improve gr reset on GF100 and newer. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/sec2: dump tracepc info on haltBen Skeggs2022-11-093-0/+21
| | | | | | | | | | | | | | - useful to distinguish between different issues. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/acr: use common falcon HS FW code for ACR FWsBen Skeggs2022-11-0930-856/+648
| | | | | | | | | | | | | | | | | | | | | | Adds context binding and support for FWs with a bootloader to the code that was added to load VPR scrubber HS binaries, and ports ACR over to using all of it. - gv100 split from gp108 to handle FW exit status differences Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fb/gp102-: unlock VPR right after devinitBen Skeggs2022-11-093-9/+16
| | | | | | | | | | | | | | | | | | | | Under memory load, instmem allocations could end up in the regions of VRAM that are inaccessible right after boot, and be corrupted after a suspend/resume cycle as a result of being restored before booting the mem unlock firmware. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fb: handle sysmem flush page from common codeBen Skeggs2022-11-0915-83/+80
| | | | | | | | | | | | | | - also executes pre-DEVINIT, so early boot is able to DMA sysmem Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/flcn: new code to load+boot simple HS FWs (VPR scrubber)Ben Skeggs2022-11-0910-66/+594
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the start of common interfaces to load and boot the HS binaries provided by NVIDIA that enable the usage of GR. ACR already handles most of this, but it's very much tied into ACR's init process, and there's other code that could benefit from reusing a lot of this stuff too (ie. VBIOS DEVINIT/PreOS, VPR scrubber). The VPR scrubber code is fairly independent, and a good first target. - adds better debug output to fw loading process, to ease bring-up/debug v2: - whitespace, 0->false Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/flcn: rework falcon resetBen Skeggs2022-11-0916-143/+185
| | | | | | | | | | | | | | | | | | Mostly preparation to fit in Ampere changes, but should result in reset sequences a lot closer to RM's, and perhaps help out with the issues we sometimes see reported in this area. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/sec2: switch to newer style interrupt handlerBen Skeggs2022-11-094-13/+26
| | | | | | | | | | | | | | Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/sec2: unload RTOS before tearing down WPRBen Skeggs2022-11-0911-51/+91
| | | | | | | | | | | | | | | | | | | | | | Reset regs won't be available on Ampere while SEC2 RTOS is running, and we're apparently supposed to be doing this on earlier GPUs too. v2: - fixed some excessive indentation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/pmu/gm20b,gp10b: boot RTOS from PMU initBen Skeggs2022-11-099-60/+92
| | | | | | | | | | | | | | Cleanup before falcon changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/pmu: move init() falcon reset to non-nvfw codeBen Skeggs2022-11-098-70/+27
| | | | | | | | | | | | | | | | | | | | | | | | Cleanup before falcon changes. - fixes (attempt at?) reset of pmu while rtos is running, on gm20b v2: - remove extra whitespace Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/pmu: move preinit() falcon reset to devinitBen Skeggs2022-11-092-13/+7
| | | | | | | | | | | | | | Cleanup before falcon changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/gsp: add funcsBen Skeggs2022-11-095-7/+20
| | | | | | | | | | | | | | Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo/ga100-: initial supportBen Skeggs2022-11-0913-276/+610
| | | | | | | | | | | | | | | | - replaces the hacked-up version that existed solely to support TTM v2. remove earlier hack preventing use of non-stall intr for fences Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau/ce/ga100-: initial supportBen Skeggs2022-11-098-0/+144
| | | | | | | | | | | | | | | | | | - replaces the hacked-up version that existed solely to support TTM - noop until the next commit, adding proper support for ampere host v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau/fifo: add new channel classesBen Skeggs2022-11-0963-1763/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exposes a bunch of the new features that became possible as a result of the earlier commits. DRM will build on this in the future to add support for features such as SCG ("async compute") and multi-device rendering, as part of the work necessary to be able to write a half- decent vulkan driver - finally. For the moment, this just crudely ports DRM to the API changes. - channel class interfaces now the same for all HW classes - channel group class exposed (SCG) - channel runqueue selector exposed (SCG) - channel sub-device id control exposed (multi-device rendering) - channel names in logging will reflect creating process, not fd owner - explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer - drm is smarter about determining the appropriate channel class to use Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add new engine object handlingBen Skeggs2022-11-0922-228/+94
| | | | | | | | | | | | | | Simplifies the GPU-specific code, completing the switch to newer HALs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add new engine context handlingBen Skeggs2022-11-0939-930/+382
| | | | | | | | | | | | | | | | | | Builds on the context tracking that was added earlier. - marks engine context PTEs as 'priv' where possible Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add RAMFC info to nvkm_chan_funcBen Skeggs2022-11-0929-321/+488
| | | | | | | | | | | | | | | | - adds support for specifying SUBDEVICE_ID for channel - rounds non-power-of-two GPFIFO sizes down, rather than up Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add USERD info to nvkm_chan_funcBen Skeggs2022-11-0923-115/+157
| | | | | | | | | | | | | | | | | | | | And use it to cleanup multiple implementations of almost the same thing. - prepares for non-polled / client-provided USERD - only zeroes relevant "registers", rather than entire USERD Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add RAMIN info to nvkm_chan_funcBen Skeggs2022-11-0916-20/+64
| | | | | | | | | | | | | | Currently provided by {chan,dma,gpfifo}*.c, and those are going away. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add common runlist controlBen Skeggs2022-11-0935-505/+284
| | | | | | | | | | | | | | | | | | - less dependence on waiting for runlist updates, on GPUs that allow it - supports runqueue selector in RAMRL entries - completes switch to common runl/cgrp/chan topology info Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add common channel recoveryBen Skeggs2022-11-0919-605/+559
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That sure was fun to untangle. - handled per-runlist, rather than globally - more straight-forward process in general - various potential SW/HW races have been fixed - fixes lockdep issues that were present in >=gk104's prior implementation - volta recovery now actually stands a chance of working - volta/turing waiting for PBDMA idle before engine reset - turing using hw-provided TSG info for CTXSW_TIMEOUT Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: kill channel on NV_PPBDMA_INTR_1_CTXNOTVALIDBen Skeggs2022-11-093-0/+30
| | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: kill channel on a selection of PBDMA errorsBen Skeggs2022-11-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | A bunch of these can be handled in such a way that the channel can continue, however, any of these are a pretty decent sign something has gone horribly wrong, and the safest option is to disable the channel. This is a bit of a hack, we will want to handle these individually and dump relevant debug info for each at some point. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add chan/cgrp preempt()Ben Skeggs2022-11-0919-86/+102
| | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add chan start()/stop()Ben Skeggs2022-11-0927-108/+191
| | | | | | | | | | | | | | | | | | - nvkm_chan_error() built on top, stops channel and sends 'killed' event - removes an odd double-bashing of channel enable regs on kepler and up - pokes doorbell on turing and up, after enabling channel Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add chan bind()/unbind()Ben Skeggs2022-11-0917-37/+115
| | | | | | | | | | | | | | - stops programming (non-existent) runl id field on bind(), from maxwell Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add runlist block()/allow()Ben Skeggs2022-11-0913-14/+95
| | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add runlist wait()Ben Skeggs2022-11-0915-32/+102
| | | | | | | | | | | | | | | | - adds g8x/turing registers, which were missing before - switches fermi to polled wait, like later hw (see: 4f2fc25c0f8bc...) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add new engine context trackingBen Skeggs2022-11-097-10/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | Channel groups have somewhat more complicated requirements than what we currently support. An engine context is shared between all channels in a channel group, VEID/subctx support (later) brings per-VEID components, and we need to track an individual channel's engine context pointers. This commit adds the structures and refcounting to support the above, wrapping the prior implementation for the moment. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add new channel lookup interfacesBen Skeggs2022-11-0928-132/+166
| | | | | | | | | | | | | | | | | | | | | | - supports per-runlist CHIDs - channel group lock held across reference, rather than global lock v2: - remove unnecessary parenthesis Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: merge mmu fault handlers togetherBen Skeggs2022-11-0914-335/+183
| | | | | | | | | | | | | | | | | | | | | | | | After updating GF100 implementation from the GK104/TU102 ones, and using the new runlist/engine topology info, all three handlers become (almost) identical. - there's a temporary kludge to call through to the HW-specific recovery - engine fault mapping info determined at load time, not on every fault Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: move PBDMA intr to runqBen Skeggs2022-11-098-102/+84
| | | | | | | | | | | | | | - merges gf100/gk104- NV_PFIFO_INTR_0_PBDMA and NV_PPBDMA_INTR_0 code Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: move PBDMA init to runqBen Skeggs2022-11-0915-74/+36
| | | | | | | | | | | | | | | | | | - bumps pbdma timeout to value RM uses on newer HW - bumps fb timeout to max from boot default - one/both of these greatly improves stability on // piglit runs Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: program NV_PFIFO_FB_TIMEOUT on initBen Skeggs2022-11-092-0/+2
| | | | | | | | | | | | | | | | NVGPU and RM both program this value. Fixes a bunch of random hangs running parallel piglit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau/fifo: tidy global PBDMA initBen Skeggs2022-11-0914-32/+52
| | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* | drm/nouveau/fifo: tidy up non-stall intr handlingBen Skeggs2022-11-0920-118/+93
| | | | | | | | | | | | | | | | - removes a layer of indirection in the intr handling - prevents non-stall ctrl racing with unknown intrs Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: use explicit intr interfacesBen Skeggs2022-11-0917-89/+105
| | | | | | | | | | | | | | More control, and shallower call-chain to get to the point. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: use runlist engine info to lookup engine classesBen Skeggs2022-11-0922-146/+35
| | | | | | | | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add cgrp, have all channels be part of oneBen Skeggs2022-11-0913-18/+231
| | | | | | | | | | | | | | | | | | | | Engine context tracking will move to nvkm_cgrp in later commits, so we create SW-only channel groups on HW without support for them. - switches to nvkm_chid for TSG/channel ID allocation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: expose per-runlist CHID informationBen Skeggs2022-11-098-21/+80
| | | | | | | | | | | | | | | | | | | | DRM uses this to setup fence-related items. - nouveau_chan.runlist will always be "0" for the moment, not an issue as GPUs prior to ampere have system-wide channel IDs, Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: expose runlist topology info on all chipsetsBen Skeggs2022-11-0917-116/+81
| | | | | | | | | | | | | | | | | | Previously only available from Kepler onwards. - also fixes the info() queries causing fifo init()/fini() unnecessarily Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add common runlist/engine topologyBen Skeggs2022-11-0926-43/+583
| | | | | | | | | | | | | | | | | | | | | | | | Creates an nvkm_runl for each runlist on the GPU, and an nvkm_engn for each engine that is reachable from a runlist. - basically what gk104- already does, but extended to all chips - adds per-runlist CHID allocators (Ampere) - splits g98/gt2xx out from g84 (different target engines) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add runqBen Skeggs2022-11-0917-27/+153
| | | | | | | | | | | | | | | | Creates an nvkm_runq for each PBDMA, these will be associated with the relevant runlist(s) later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: add chid allocatorBen Skeggs2022-11-0926-21/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | We need to be able to allocate TSG IDs as well as channel IDs, also, Ampere has per-runlist channel IDs. - holds per-ID private data, which will be used for/to protect lookup - holds an nvkm_event which will be used for events tied to IDs - not used yet beyond setup, and switching use of "fifo->nr - 1" for channel ID mask to "chid->mask" Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
* | drm/nouveau/fifo: merge gk104_fifo_func into nvkm_host_funcBen Skeggs2022-11-0914-111/+219
| | | | | | | | | | | | | | | | | | This makes it easier to transition everything. - a couple of function renames for collisions Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
generated by cgit (git 2.34.1) at 2025-02-24 15:07:23 +0000