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path: root/drivers/gpu/drm
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* drm/amdgpu: save the reset dump register value for devcoredumpSomalapuram Amaranath2022-06-063-3/+11
| | | | | | | | | | Allocate memory for register value and use the same values for devcoredump. v1 -> v2: Change krealloc_array() to kmalloc_array() v2 -> v3: Fix alignment Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> Reviewed-by: Shashank Sharma <Shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: program PSR2 DPCD ConfigurationDavid Zhang2022-06-062-2/+34
| | | | | | | | | | | | | [Why] To support PSR2 Source DPCD configuration [How] Update the PSR2 Source DPCD settings while the PSR2 enabled Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: revise Start/End SDP dataDavid Zhang2022-06-061-2/+27
| | | | | | | | | | | | | | | | | | [why & how] We need to implement the VSC packet rev4 that is required by PSRSU. Follow the eDP 1.5 spec pg. 257 changes in v2: ------------------- - set vsc packet rev2 for PSR1 Cc: Chandan Vurdigerenataraj <chandan.vurdigerenataraj@amd.com> Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: update GSP1 generic info packet for PSRSUDavid Zhang2022-06-061-0/+15
| | | | | | | | | | | | [why & how] Based on PSRSU specification, every selective update frame need to use two SDP to indicate the frame active range. So we occupy another GSP1 for PSRSU execution. Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: combine dirty rectangles in DMUB FWDavid Zhang2022-06-062-0/+59
| | | | | | | | | | | | | | | | | [why] In PSR-SU design, the DMUB FW handles the combination of multiple dirty rectangles. [how] - create DC dmub update dirty rectangle helper which sends the dirty rectangles per pipe from DC to DMUB, and DMUB FW will handle to combine the dirty RECTs - call the helper from DC commit plane update function. Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: feed PSR-SU as psr version to dmub FWDavid Zhang2022-06-061-0/+3
| | | | | | | | | | | [why & how] set psr version as PSR-SU in kernel-FW interface function to ensure the correct dmub command parameter is fed into FW. Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: align dmub cmd header to latest dmub FW to support PSR-SUDavid Zhang2022-06-031-5/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | [why] PSR-SU is implemented in upstreamed dmub FW but not enabled on DM and DC. We'd add necessary and missing definitions in dmub cmd header to align w/ the up-to-date DMUB FW for PSR-SU support. [how] Add definitions and items below into dmub cmd header: - DMUB psr version enumeration for PSR-SU - dirty rectangle structure - psr debug flag of forcing full frame update - dmub command of updating dirty rectangle and cursor infor - dmub psr command type of setting sink vtotal in PSR active - dmub psr su debug flags structure - dmub cmd structure for - updating dirty rectangle - cursor infor - setting sink vtotal - dmub ringbuffer command items Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/display/dc: Add ACP_DATA registerAlan Liu2022-06-032-0/+3
| | | | | | | | | Define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA Define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK/SHIFT Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCNAlex Deucher2022-06-031-0/+4
| | | | | | | | | | | | | Protect remove_hpo_dp_link_enc_from_ctx() and release_hpo_dp_link_enc() with CONFIG_DRM_AMD_DC_DCN as the functions are only called from code that is protected by CONFIG_DRM_AMD_DC_DCN. Fixes build fail with -Werror=unused-function. Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for DCN32/321") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
* drm/amd/display: Add ODM seamless boot supportDuncan Ma2022-06-035-3/+38
| | | | | | | | | | Revised validation logic when marking for seamless boot. Init resources accordingly when Pre-OS has ODM enabled. Reset ODM when transitioning Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set odm accordingly upon commit. Signed-off-by: Duncan Ma <duncan.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement DTBCLK ref switching on dcn32Alvin Lee2022-06-0310-31/+118
| | | | | | | | | | | [WHY & HOW] Implements DTB ref clock switching with reg key default to OFF. Refactors dccg DTBCLK logic to not store redundant state information dccg. Also removes duplicated functions that should be inherited from other dcn versions. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Match dprefclk with clk registersSamson Tam2022-06-031-3/+6
| | | | | | | Update base.dprefclk_khz to match result from dcn32_dump_clk_registers() Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: cleaning up smu_if to add future flexibilityMartin Leung2022-06-034-16/+78
| | | | | | | | This commit cleans up code that uses old variables and adds some SMU interfaces for future flexibility. Signed-off-by: Martin Leung <Martin.Leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: update disp pattern generator routine for DCN30Aurabindo Pillai2022-06-031-31/+2
| | | | | Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Updates for OTG and DCCG clocksSamson Tam2022-06-033-1/+9
| | | | | | | Use DTBCLK for valid pixel clock generation Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: FCLK P-state support updatesChaitanya Dhere2022-06-032-5/+7
| | | | | | | | | | | | | | | [Why] Previously we used to send FCLK P-state enable messages upon each call to update_clocks based on dml output. This resulted in increased message transactions between DC and PMFW. [How] Update the code to check safe_to_lower status and send the message based on dml input only on boot. This reduces message transactions. Also remove other unwanted code based on current code status. Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Introduce new update_clocks logicJun Lei2022-06-031-52/+73
| | | | | | | | | | | | | | | [why] DCN has sidebands to control some clocks, it is useful for clk_mgr to always update the clocks it explicitly controls rather than skip them because it enables more configurations to work without SMU [how] only skip handling clocks where SMU manages the frequency for clocks with DENTIST sideband (DISP/DPP), only skip the voltage request when SMU not available, but otherwise proceed normally Signed-off-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: set link fec status during init for DCN32Jingwen Zhu2022-06-031-1/+5
| | | | | | | We can now enable FEC. Signed-off-by: Jingwen Zhu <Jingwen.Zhu@github.amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add new pixel rate programmingJun Lei2022-06-0310-8/+95
| | | | | | | | | | | | | | [why] New dividers in DCCG need to be programmed depending on encoder/stream type since pixels per clock in OTG/DIO is different DIO also needs additional programming depending on pixels per clock Signed-off-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
* drm/amd/display: Remove W/A for ODM memory pinsAlvin Lee2022-06-032-2/+2
| | | | | | | | | [Description] By default we can now set ODM_MEM_VBLANK_PWR_MODE=1 Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix up comment in amdgpu_device_asic_has_dc_support()Alex Deucher2022-06-031-1/+1
| | | | | | | | LVDS support was implemented in DC a while ago. Just DAC support is left to do. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: do not override CURSOR_REQ_MODE when SubVP is not enabledSamson Tam2022-06-031-2/+5
| | | | | | | | | | | | | | | | | | | [Why] HUBP_UNBOUNDED_REQ_MODE and CURSOR_REQ_MODE are normally set together. In hubp32_prepare_subvp_buffering() call, CURSOR_REQ_MODE is set based on whether SubVP is enabled or not. For non MPO case, both REQ_MODE registers are set to 1. But since SubVP is not enabled, then CURSOR_REQ_MODE is set to 0, overriding the previous value. [How] Do not set CURSOR_REQ_MODE to 0 if SubVP is not enabled. This will allow CURSOR_REQ_MODE to stay as 1 in the non MPO case. Add note to follow up and check case for single pipe MPO and SubVP enabled as this would cause both REQ_MODE registers to be set to 0 but SubVP enabled would override CURSOR_REQ_MODE to 1. Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: delete duplicate condition in gfx_v11_0_soft_reset()Dan Carpenter2022-06-031-13/+11
| | | | | | | | We know that "grbm_soft_reset" is true because we're already inside an if (grbm_soft_reset) condition. No need to test again. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: use new register offsets for smu_cmn.cAlex Deucher2022-06-031-70/+7
| | | | | | | | | Use the per asic offsets so the we don't have to have asic specific logic in the common code. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: change dsc image width cap for dcn32 and dcn321Dillon Varone2022-06-032-0/+6
| | | | | | | Set appropriate caps for DCN3.2.x. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: add SMU mailbox registers in SMU contextAlex Deucher2022-06-0317-0/+86
| | | | | | | | | So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common code. Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Disable DTB Ref Clock Switching in dcn32Dillon Varone2022-06-031-0/+4
| | | | | | | | [How & Why] To be enabled once PMFW supports it. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gmc11: enable AGP apertureAlex Deucher2022-06-034-9/+11
| | | | | | | Enable the AGP aperture on chips with GMC v11. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: convert nbio_v2_3_clear_doorbell_interrupt() to IP versionAlex Deucher2022-06-031-1/+1
| | | | | | | Check IP version rather than asic type. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: set dram speed for all statesDillon Varone2022-06-032-2/+10
| | | | | | | | | | | | [WHY?] If higher states have memory speed set to 0 MT/s currently they do not get set to the highest value which can cause validation failures. [HOW?] Set unpopulated higher states to max value. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: simplify the logic in amdgpu_device_parse_gpu_info_fw()Alex Deucher2022-06-031-29/+0
| | | | | | | Drop all of the extra cases in the default case. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: convert sienna_cichlid_populate_umd_state_clk() to use IP versionAlex Deucher2022-06-031-5/+5
| | | | | | | Rather than asic type. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Halve DTB Clock Value for DCN32Fangzhi Zuo2022-06-031-1/+1
| | | | | | | | | | | | | | | | VBIOS default clock value was halved, so the hardcoded dtb value should be halved as well. dtb clock should come from SMU eventually, but now dtb clock switching is not fully supported yet in SMU. Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on SMU for dtb clock switching once available. The w/a is for DCN32 only, DCN321 should adopt the original value. Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add additional guard for FCLK pstate message for DCN321Dillon Varone2022-06-031-3/+4
| | | | | | | Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7Xiaojian Du2022-06-031-1/+7
| | | | | | | | | | | | | This patch will fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7.0. NBIO v7.7.0 uses a new reg function -- Common SDMA to allow a common doorbell range for all SDMA queues, this is different to the old NBIO version. This patch will add configuration for CSDMA and enable SDMA doorbell function. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.0Xiaojian Du2022-06-032-0/+14
| | | | | | | | | This patch will add CSDMA reg offsets for NBIO v7.7.0 Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Acked-by: Roman Li <roman.li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add apu sequence in the imu v11Huang Rui2022-06-032-4/+9
| | | | | | | | APU required to issue the enable GFX IMU message after IMU reset. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu functionHuang Rui2022-06-037-1/+44
| | | | | | | | GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/pm: update MP v13_0_4 smu message register marcoHuang Rui2022-06-031-0/+20
| | | | | | | | | | Update MP v13_0_4 register macro for SMU message v2: squash in missed case (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add mmhub v3_0_1 ip blockHuang Rui2022-06-034-1/+589
| | | | | | | | | | This adds mmhub v3_0_1 ip block support v2: rebase (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add mmhub v3_0_1 headersHuang Rui2022-06-032-0/+9252
| | | | | | | | | | Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0. v2: squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: use the callback function for reset status polling on IMUHuang Rui2022-06-032-14/+24
| | | | | | | | | | | Switch to use the callback function to poll the reset status on IMU. Because it will have different sequency on other ASICs. v2: drop unused variable (Alex) Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Ensure that DMCUB fw in use is loaded by DC and not VBIOSDillon Varone2022-06-031-1/+3
| | | | | | | | | | | | | | | [Why?] On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads DMUB, and driver does not reload as it appears to be initialized already. [How?] Add a check for the DAL_FW bit to ensure that loaded FW is from driver and not VBIOS. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: use updated clock source init routineCharlene Liu2022-06-032-2/+2
| | | | | | | | | [why] Use correct clock source initialization routine for DCN32/321 Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Select correct DTO sourceDillon Varone2022-06-031-0/+27
| | | | | | | | | | [WHY&HOW] Change criteria for setting DTO source value, and always set it regardless of the signal type. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: print umc correctable error addressStanley.Yang2022-06-033-2/+54
| | | | | | Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: disable idle optimizationsAurabindo Pillai2022-06-031-0/+1
| | | | | | | | | Disable idle optimizations until SMU can handle them to prevent DMUB timeout and subsequent system freeze Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add missing interrupt handlers for DCN32/DCN321Aurabindo Pillai2022-06-031-1/+64
| | | | | | Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement WM table transfer for DCN32/DCN321Alvin Lee2022-06-031-0/+7
| | | | | | | | Add support for watermark table transfers. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Various DML fixes to enable higher timingsDillon Varone2022-06-033-38/+26
| | | | | | | | | | Fixes to enable higher rate timings for DCN3.2.x. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-02-24 21:59:08 +0000