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* PCI: aardvark: Move to struct pci_host_bridge IRQ mapping functionsThomas Petazzoni2017-10-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ mapping can be done automatically by PCI core code through the pci_assign_irq() function instead of resorting to arch-specific implementation callbacks to carry out the same task which force PCI host bridge drivers implementation to implement per-arch kludges to carry out a task that is inherently architecture agnostic. Commit 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()") was assuming all PCI host controller drivers had been converted to use ->map_irq(), but that wasn't the case: pci-aardvark had not been converted. Due to this, it broke the support for legacy PCI interrupts when using the pci-aardvark driver (used on Marvell Armada 3720 platforms). In order to fix this, we make sure the ->map_irq and ->swizzle_irq fields of pci_host_bridge are properly filled in. Fixes: 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()") Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v4.13+
* Revert "PCI: tegra: Do not allocate MSI target memory"Thierry Reding2017-10-101-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d7bd554f27c942e6b8b54100b4044f9be1038edf. It turns out that Tegra20 has a bug in the implementation of the MSI target address register (which is worked around by the existence of the struct tegra_pcie_soc.msi_base_shift parameter) that restricts the MSI target memory to the lower 32 bits of physical memory on that particular generation. The offending patch causes a regression on TrimSlice, which is a Tegra20-based device and has a PCI network interface card. An initial, simpler fix was to change the MSI target address for Tegra20 only, but it was pointed out that the offending commit also prevents the use of 32-bit only MSI capable devices, even on later chips. Technically this was never guaranteed to work with the prior code in the first place because the allocated page could have resided beyond the 4 GiB boundary, but it is still possible that this could've introduced a regression. The proper fix that was settled on is to select a fixed address within the lowest 32 bits of physical address space that is otherwise unused, but testing of that patch has provided mixed results that are not fully understood yet. Given all of the above and the relative urgency to get this fixed in v4.13, revert the offending commit until a universal fix is found. Fixes: d7bd554f27c9 ("PCI: tegra: Do not allocate MSI target memory") Reported-by: Tomasz Maciej Nowak <tmn505@gmail.com> Reported-by: Erik Faye-Lund <kusmabite@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # 4.13.x
* Merge tag 'pci-v4.14-changes' of ↵Linus Torvalds2017-09-0820-471/+1334
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add enhanced Downstream Port Containment support, which prints more details about Root Port Programmed I/O errors (Dongdong Liu) - add Layerscape ls1088a and ls2088a support (Hou Zhiqiang) - add MediaTek MT2712 and MT7622 support (Ryder Lee) - add MediaTek MT2712 and MT7622 MSI support (Honghui Zhang) - add Qualcom IPQ8074 support (Varadarajan Narayanan) - add R-Car r8a7743/5 device tree support (Biju Das) - add Rockchip per-lane PHY support for better power management (Shawn Lin) - fix IRQ mapping for hot-added devices by replacing the pci_fixup_irqs() boot-time design with a host bridge hook called at probe-time (Lorenzo Pieralisi, Matthew Minter) - fix race when enabling two devices that results in upstream bridge not being enabled correctly (Srinath Mannam) - fix pciehp power fault infinite loop (Keith Busch) - fix SHPC bridge MSI hotplug events by enabling bus mastering (Aleksandr Bezzubikov) - fix a VFIO issue by correcting PCIe capability sizes (Alex Williamson) - fix an INTD issue on Xilinx and possibly other drivers by unifying INTx IRQ domain support (Paul Burton) - avoid IOMMU stalls by marking AMD Stoney GPU ATS as broken (Joerg Roedel) - allow APM X-Gene device assignment to guests by adding an ACS quirk (Feng Kan) - fix driver crashes by disabling Extended Tags on Broadcom HT2100 (Extended Tags support is required for PCIe Receivers but not Requesters, and we now enable them by default when Requesters support them) (Sinan Kaya) - fix MSIs for devices that use phantom RIDs for DMA by assuming MSIs use the real Requester ID (not a phantom RID) (Robin Murphy) - prevent assignment of Intel VMD children to guests (which may be supported eventually, but isn't yet) by not associating an IOMMU with them (Jon Derrick) - fix Intel VMD suspend/resume by releasing IRQs on suspend (Scott Bauer) - fix a Function-Level Reset issue with Intel 750 NVMe by waiting longer (up to 60sec instead of 1sec) for device to become ready (Sinan Kaya) - fix a Function-Level Reset issue on iProc Stingray by working around hardware defects in the CRS implementation (Oza Pawandeep) - fix an issue with Intel NVMe P3700 after an iProc reset by adding a delay during shutdown (Oza Pawandeep) - fix a Microsoft Hyper-V lockdep issue by polling instead of blocking in compose_msi_msg() (Stephen Hemminger) - fix a wireless LAN driver timeout by clearing DesignWare MSI interrupt status after it is handled, not before (Faiz Abbas) - fix DesignWare ATU enable checking (Jisheng Zhang) - reduce Layerscape dependencies on the bootloader by doing more initialization in the driver (Hou Zhiqiang) - improve Intel VMD performance allowing allocation of more IRQ vectors than present CPUs (Keith Busch) - improve endpoint framework support for initial DMA mask, different BAR sizes, configurable page sizes, MSI, test driver, etc (Kishon Vijay Abraham I, Stan Drozd) - rework CRS support to add periodic messages while we poll during enumeration and after Function-Level Reset and prepare for possible other uses of CRS (Sinan Kaya) - clean up Root Port AER handling by removing unnecessary code and moving error handler methods to struct pcie_port_service_driver (Christoph Hellwig) - clean up error handling paths in various drivers (Bjorn Andersson, Fabio Estevam, Gustavo A. R. Silva, Harunobu Kurokawa, Jeffy Chen, Lorenzo Pieralisi, Sergei Shtylyov) - clean up SR-IOV resource handling by disabling VF decoding before updating the corresponding resource structs (Gavin Shan) - clean up DesignWare-based drivers by unifying quirks to update Class Code and Interrupt Pin and related handling of write-protected registers (Hou Zhiqiang) - clean up by adding empty generic pcibios_align_resource() and pcibios_fixup_bus() and removing empty arch-specific implementations (Palmer Dabbelt) - request exclusive reset control for several drivers to allow cleanup elsewhere (Philipp Zabel) - constify various structures (Arvind Yadav, Bhumika Goyal) - convert from full_name() to %pOF (Rob Herring) - remove unused variables from iProc, HiSi, Altera, Keystone (Shawn Lin) * tag 'pci-v4.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (170 commits) PCI: xgene: Clean up whitespace PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset PCI: xgene: Fix platform_get_irq() error handling PCI: xilinx-nwl: Fix platform_get_irq() error handling PCI: rockchip: Fix platform_get_irq() error handling PCI: altera: Fix platform_get_irq() error handling PCI: spear13xx: Fix platform_get_irq() error handling PCI: artpec6: Fix platform_get_irq() error handling PCI: armada8k: Fix platform_get_irq() error handling PCI: dra7xx: Fix platform_get_irq() error handling PCI: exynos: Fix platform_get_irq() error handling PCI: iproc: Clean up whitespace PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP PCI: iproc: Add 500ms delay during device shutdown PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag() PCI/AER: Reformat AER register definitions iommu/vt-d: Prevent VMD child devices from being remapping targets x86/PCI: Use is_vmd() rather than relying on the domain number ...
| * Merge branch 'pci/trivial' into nextBjorn Helgaas2017-09-072-2/+2
| |\ | | | | | | | | | | | | | | | | | | * pci/trivial: PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
| | * PCI: Fix typos and whitespace errorsBjorn Helgaas2017-09-012-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/misc' into nextBjorn Helgaas2017-09-072-6/+5
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/misc: PCI: Fix PCIe capability sizes PCI: Convert to using %pOF instead of full_name() PCI: Constify endpoint pci_epf_type device_type PCI: Constify bin_attribute structures PCI: Constify hotplug pci_device_id structures PCI: Constify hotplug attribute_group structures PCI: Constify label attribute_group structures PCI: Constify sysfs attribute_group structures
| | * | PCI: Convert to using %pOF instead of full_name()Rob Herring2017-08-242-6/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a custom printf format specifier, convert users of full_name() to use %pOF instead. This is preparation for removing storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tyrel Datwyler <tyreld@linux.vnet.ibm.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au>
| * | Merge branch 'pci/host-xilinx' into nextBjorn Helgaas2017-09-073-45/+28
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-xilinx: PCI: xilinx-nwl: Fix platform_get_irq() error handling PCI: xilinx: Allow build on MIPS platforms PCI: xilinx: Don't enable config completion interrupts PCI: xilinx: Unify INTx & MSI interrupt decode PCI: xilinx-nwl: Translate INTx range to hwirqs 0-3 PCI: xilinx: Translate INTx range to hwirqs 0-3
| | * | PCI: xilinx-nwl: Fix platform_get_irq() error handlingFabio Estevam2017-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com>
| | * | PCI: xilinx: Allow build on MIPS platformsPaul Burton2017-08-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the xilinx-pcie driver to be built on MIPS platforms which make use of generic PCI drivers rather than legacy MIPS-specific interfaces. This is used on the MIPS Boston development board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
| | * | PCI: xilinx: Don't enable config completion interruptsPaul Burton2017-08-161-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Xilinx AXI bridge for PCI Express device provides interrupts indicating the completion of config space accesses. We have previously enabled/unmasked them but do nothing with them besides acknowledge them. Leave the interrupts masked in order to avoid servicing a large number of pointless interrupts during boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
| | * | PCI: xilinx: Unify INTx & MSI interrupt decodePaul Burton2017-08-161-33/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The INTx & MSI interrupt decode paths duplicated a fair bit of common functionality. They also strictly handled interrupts in order of INTx then MSI, so if both types of interrupt were to be asserted simultaneously and the MSI interrupt were first in the FIFO then the INTx code would read it & ignore it before the MSI code then had to read it again, wasting the original FIFO read. Unify the INTx & MSI decode in order to reduce that duplication & allow a single FIFO read to be performed for each interrupt regardless of its type. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
| | * | PCI: xilinx-nwl: Translate INTx range to hwirqs 0-3Paul Burton2017-08-161-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The devicetree binding documentation for the Xilinx NWL PCIe root port bridge shows an example which uses an interrupt-map property to map PCI INTx interrupts to hardware IRQ numbers 1-4. The driver creates an IRQ domain with size 4, which therefore covers the hwirq range 0-3. This means that if we attempt to make use of the INTD interrupt then we're likely to hit a WARN() in irq_domain_associate() because INTD, or hwirw=4, is outside of the range covered by the IRQ domain. irq_domain_associate() will then return -EINVAL and we'll be unable to make use of INTD. Fix this by making use of the pci_irqd_intx_xlate() helper function to translate the 1-4 range used in the DT to a 0-3 range used within the driver, and stop adding 1 to decoded hwirq numbers. Whilst cleaning up INTx handling we make use of the new PCI_NUM_INTX macro & drop the custom INTX definitions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
| | * | PCI: xilinx: Translate INTx range to hwirqs 0-3Paul Burton2017-08-161-3/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pcie-xilinx driver creates an IRQ domain of size 4 for legacy PCI INTx interrupts, which at first glance seems reasonable since there are 4 possible such interrupts. Unfortunately the driver then proceeds to use the range 1-4 as the hwirq numbers for INTA-INTD, causing warnings & broken interrupts when attempting to use INTD/hwirq=4 due to it being beyond the range of the IRQ domain: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:365 irq_domain_associate+0x170/0x220 error: hwirq 0x4 is too large for dummy Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.12.0-rc5-00126-g19e1b3a10aad-dirty #427 Stack : 0000000000000000 0000000000000004 0000000000000006 ffffffff8092c78a 0000000000000061 ffffffff8018bf60 0000000000000000 0000000000000000 ffffffff8088c287 ffffffff80811d18 a8000000ffc60000 ffffffff80926678 0000000000000001 0000000000000000 ffffffff80887880 ffffffff80960000 ffffffff80920000 ffffffff801e6744 ffffffff80887880 a8000000ffc4f8f8 000000000000089c ffffffff8018d260 0000000000010000 ffffffff80811d18 0000000000000000 0000000000000001 0000000000000000 0000000000000000 0000000000000000 a8000000ffc4f840 0000000000000000 ffffffff8042cf34 0000000000000000 0000000000000000 0000000000000000 0000000000040c00 0000000000000000 ffffffff8010d1c8 0000000000000000 ffffffff8042cf34 ... Call Trace: [<ffffffff8010d1c8>] show_stack+0x80/0xa0 [<ffffffff8042cf34>] dump_stack+0xd4/0x110 [<ffffffff8013ea98>] __warn+0xf0/0x108 [<ffffffff8013eb14>] warn_slowpath_fmt+0x3c/0x48 [<ffffffff80196528>] irq_domain_associate+0x170/0x220 [<ffffffff80196bf0>] irq_create_mapping+0x88/0x118 [<ffffffff801976a8>] irq_create_fwspec_mapping+0xb8/0x320 [<ffffffff80197970>] irq_create_of_mapping+0x60/0x70 [<ffffffff805d1318>] of_irq_parse_and_map_pci+0x20/0x38 [<ffffffff8049c210>] pci_fixup_irqs+0x60/0xe0 [<ffffffff8049cd64>] xilinx_pcie_probe+0x28c/0x478 [<ffffffff804e8ca8>] platform_drv_probe+0x50/0xd0 [<ffffffff804e73a4>] driver_probe_device+0x2c4/0x3a0 [<ffffffff804e7544>] __driver_attach+0xc4/0xd0 [<ffffffff804e5254>] bus_for_each_dev+0x64/0xa8 [<ffffffff804e5e40>] bus_add_driver+0x1f0/0x268 [<ffffffff804e8000>] driver_register+0x68/0x118 [<ffffffff801001a4>] do_one_initcall+0x4c/0x178 [<ffffffff808d3ca8>] kernel_init_freeable+0x204/0x2b0 [<ffffffff80730b68>] kernel_init+0x10/0xf8 [<ffffffff80106218>] ret_from_kernel_thread+0x14/0x1c Fix this by making use of the new pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 range suitable for the IRQ domain of size 4, and stop adding 1 to the hwirq number decoded from the interrupt FIFO which is already in the range 0-3. Whilst we're here we switch to using PCI_NUM_INTX rather than the magic number 4, making it clearer what the 4 means. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
| * | Merge branch 'pci/host-xgene' into nextBjorn Helgaas2017-09-072-22/+21
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-xgene: PCI: xgene: Clean up whitespace PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset PCI: xgene: Fix platform_get_irq() error handling
| | * | PCI: xgene: Clean up whitespaceBjorn Helgaas2017-09-071-19/+18
| | | | | | | | | | | | | | | | | | | | Use tabs (not spaces) for indentation. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offsetBjorn Helgaas2017-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently the PCIe capability is at address 0x40 in config space of X-Gene v1 Root Ports. Add a definition of that and use the generic PCI_EXP_RTCTL offset into the capability. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: xgene: Fix platform_get_irq() error handlingFabio Estevam2017-09-071-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Duc Dang <dhdang@apm.com>
| * | Merge branch 'pci/host-vmd' into nextBjorn Helgaas2017-09-071-2/+17
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-vmd: iommu/vt-d: Prevent VMD child devices from being remapping targets x86/PCI: Use is_vmd() rather than relying on the domain number x86/PCI: Move VMD quirk to x86 fixups MAINTAINERS: Add Jonathan Derrick as VMD maintainer PCI: vmd: Remove IRQ affinity so we can allocate more IRQs PCI: vmd: Free up IRQs on suspend path PCI: vmd: Assign vector zero to all bridges PCI: vmd: Reserve IRQ pre-vector for better affinity
| | * | PCI: vmd: Remove IRQ affinity so we can allocate more IRQsKeith Busch2017-08-301-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VMD hardware has to share its vectors among child devices in its PCI domain so we should allocate as many as possible rather than just ones that can be affinitized. pci_alloc_irq_vectors_affinity() limits the number of affinitized IRQs to the number of present CPUs (see irq_calc_affinity_vectors()). But we'd prefer to have more vectors, even if they aren't distributed across the CPUs, so use pci_alloc_irq_vectors() instead. Reported-by: Brad Goodman <Bradley.Goodman@dell.com> Signed-off-by: Keith Busch <keith.busch@intel.com> [bhelgaas: add irq_calc_affinity_vectors() reference to changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: vmd: Free up IRQs on suspend pathScott Bauer2017-08-141-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Free up the IRQs we request on the suspend path and reallocate them on the resume path. Fixes this error: CPU 111 disable failed: CPU has 9 vectors assigned and there are only 0 available. Error taking CPU111 down: -34 Non-boot CPUs are not disabled Enabling non-boot CPUs ... Signed-off-by: Scott Bauer <scott.bauer@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com>
| | * | PCI: vmd: Assign vector zero to all bridgesKeith Busch2017-08-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't want slower IRQ handlers impacting faster devices that happen to be assigned the same VMD interrupt vector. The driver was trying to separate such devices by checking if MSI-X wasn't used, but really we just don't want endpoint devices to share with bridges. Most bridges may use MSI currently, so that criteria happened to work, but newer ones may use MSI-X, so this patch explicitly checks the device type when choosing a vector. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: vmd: Reserve IRQ pre-vector for better affinityKeith Busch2017-08-031-2/+10
| | |/ | | | | | | | | | | | | | | | | | | The driver has a special purpose for the VMD device's first IRQ, so this one shouldn't be considered for IRQ affinity. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/host-tegra' into nextBjorn Helgaas2017-09-071-3/+3
| |\ \ | | | | | | | | | | | | | | | | * pci/host-tegra: PCI: tegra: Explicitly request exclusive reset control
| | * | PCI: tegra: Explicitly request exclusive reset controlPhilipp Zabel2017-08-031-3/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com>
| * | Merge branch 'pci/host-rockchip' into nextBjorn Helgaas2017-09-071-143/+281
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-rockchip: PCI: rockchip: Fix platform_get_irq() error handling PCI: rockchip: Umap IO space if probe fails PCI: rockchip: Remove IRQ domain if probe fails PCI: rockchip: Disable vpcie0v9 if resume_noirq fails PCI: rockchip: Clean up PHY if driver probe or resume fails PCI: rockchip: Factor out rockchip_pcie_deinit_phys() PCI: rockchip: Factor out rockchip_pcie_disable_clocks() PCI: rockchip: Factor out rockchip_pcie_enable_clocks() PCI: rockchip: Factor out rockchip_pcie_setup_irq() PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders PCI: rockchip: Use PCI_NUM_INTX PCI: rockchip: Explicitly request exclusive reset control dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model dt-bindings: PCI: rockchip: Convert to per-lane PHY model arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339 PCI: rockchip: Idle inactive PHY(s) phy: rockchip-pcie: Reconstruct driver to support per-lane PHYs PCI: rockchip: Add per-lane PHY support PCI: rockchip: Factor out rockchip_pcie_get_phys() PCI: rockchip: Control optional 12v power supply dt-bindings: PCI: rockchip: Add vpcie12v-supply for Rockchip PCIe controller
| | * | PCI: rockchip: Fix platform_get_irq() error handlingFabio Estevam2017-09-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
| | * | PCI: rockchip: Umap IO space if probe failsJeffy Chen2017-08-291-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Call pci_unmap_iospace() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Remove IRQ domain if probe failsJeffy Chen2017-08-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Call irq_domain_remove() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Disable vpcie0v9 if resume_noirq failsJeffy Chen2017-08-291-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable vpcie0v9 regulator if resume_noirq fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Clean up PHY if driver probe or resume failsShawn Lin2017-08-291-17/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Factor out rockchip_pcie_deinit_phys()Shawn Lin2017-08-291-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_deinit_phys() so it can be reused by rockchip_pcie_suspend_noirq() and rockchip_pcie_remove(). No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Factor out rockchip_pcie_disable_clocks()Shawn Lin2017-08-291-16/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_disable_clocks() so it can be reused by other functions. No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path so it matches the other paths. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Factor out rockchip_pcie_enable_clocks()Shawn Lin2017-08-291-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Factor out rockchip_pcie_setup_irq()Shawn Lin2017-08-291-35/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_setup_irq() to prepare for future bug fixes. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expandersFabio Estevam2017-08-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
| | * | PCI: rockchip: Use PCI_NUM_INTXPaul Burton2017-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Shawn Lin <shawn.lin@rock-chips.com>
| | * | PCI: rockchip: Explicitly request exclusive reset controlPhilipp Zabel2017-08-291-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
| | * | PCI: rockchip: Idle inactive PHY(s)Shawn Lin2017-08-281-2/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the status of all lanes and idle the inactive one(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: always set lanes_map, even for legacy_phy case] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: rockchip: Add per-lane PHY supportShawn Lin2017-08-281-20/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: rockchip: Factor out rockchip_pcie_get_phys()Shawn Lin2017-08-161-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We plan to introduce per-lane PHYs, so factor out rockchip_pcie_get_phys() to make it easier in the future. No functional change intended. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: rockchip: Control optional 12v power supplyShawn Lin2017-08-161-1/+24
| | |/ | | | | | | | | | | | | | | | Get vpcie12v from DT and control it if available. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/host-rcar' into nextBjorn Helgaas2017-09-071-6/+6
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-rcar: PCI: rcar: Add device tree support for r8a7743/5 PCI: rcar: Fix memory leak when no PCIe card is inserted PCI: rcar: Fix error exit path
| | * | PCI: rcar: Fix memory leak when no PCIe card is insertedHarunobu Kurokawa2017-08-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When no PCIe card is inserted, there is a memory leak as pci_free_resource_list() is not called before returning. Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
| | * | PCI: rcar: Fix error exit pathLorenzo Pieralisi2017-08-151-6/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 90634e854079 ("PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()") converted PCI root bus scan API to the new pci_scan_root_bus_bridge() API; in the process some error paths were not updated correctly which may cause memory leaks. Fix the driver error exit path reinstating the previous correct error exit behaviour. Fixes: 90634e854079 ("PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
| * | Merge branch 'pci/host-mvebu' into nextBjorn Helgaas2017-09-071-2/+1
| |\ \ | | | | | | | | | | | | | | | | * pci/host-mvebu: PCI: mvebu: Remove unneeded gpiod NULL check
| | * | PCI: mvebu: Remove unneeded gpiod NULL checkFabio Estevam2017-08-021-2/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | The gpiod API checks for NULL descriptors, so there is no need to duplicate the check in the driver. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com
| * | Merge branch 'pci/host-mediatek' into nextBjorn Helgaas2017-09-072-70/+691
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-mediatek: PCI: mediatek: Use PCI_NUM_INTX PCI: mediatek: Add MSI support for MT2712 and MT7622 PCI: mediatek: Use bus->sysdata to get host private data dt-bindings: PCI: Add support for MT2712 and MT7622 PCI: mediatek: Add controller support for MT2712 and MT7622 dt-bindings: PCI: Cleanup MediaTek binding text dt-bindings: PCI: Rename MediaTek binding PCI: mediatek: Switch to use platform_get_resource_byname() PCI: mediatek: Add a structure to abstract the controller generations PCI: mediatek: Rename port->index and mtk_pcie_parse_ports() PCI: mediatek: Use readl_poll_timeout() to wait for Gen2 training PCI: mediatek: Explicitly request exclusive reset control
| | * | PCI: mediatek: Use PCI_NUM_INTXHonghui Zhang2017-08-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch from using custom INTX_NUM macro to the generic PCI_NUM_INTX definition for the number of INTx interrupts. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: use subject/changelog from similar patches] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: mediatek: Add MSI support for MT2712 and MT7622Honghui Zhang2017-08-301-1/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT2712 and MT7622's PCIe host controller support MSI, but only 32-bit MSI addresses are supported. It connects to GIC with the same IRQ number as the INTx IRQ, so it shares the same IRQ with INTx IRQ. Add MSI support for MT2712 and MT7622. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: changes to follow rcar & tegra: rename to mtk_pcie_msi_alloc(), add mtk_pcie_msi_free(), free hwirq if irq_create_mapping() fails, call irq_dispose_mapping() from mtk_msi_teardown_irq()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
generated by cgit (git 2.34.1) at 2025-02-27 00:21:45 +0000