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* Merge tag 'irq-core-2022-10-12' of ↵Linus Torvalds2022-10-121-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull interrupt updates from Thomas Gleixner: "Core code: - Provide a generic wrapper which can be utilized in drivers to handle the problem of force threaded demultiplex interrupts on RT enabled kernels. This avoids conditionals and horrible quirks in drivers all over the place - Fix up affected pinctrl and GPIO drivers to make them cleanly RT safe Interrupt drivers: - A new driver for the FSL MU platform specific MSI implementation - Make irqchip_init() available for pure ACPI based systems - Provide a functional DT binding for the Realtek RTL interrupt chip - The usual DT updates and small code improvements all over the place" * tag 'irq-core-2022-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits) irqchip: IMX_MU_MSI should depend on ARCH_MXC irqchip/imx-mu-msi: Fix wrong register offset for 8ulp irqchip/ls-extirq: Fix invalid wait context by avoiding to use regmap dt-bindings: irqchip: Describe the IMX MU block as a MSI controller irqchip: Add IMX MU MSI controller driver dt-bindings: irqchip: renesas,irqc: Add r8a779g0 support irqchip/gic-v3: Fix typo in comment dt-bindings: interrupt-controller: ti,sci-intr: Fix missing reg property in the binding dt-bindings: irqchip: ti,sci-inta: Fix warning for missing #interrupt-cells irqchip: Allow extra fields to be passed to IRQCHIP_PLATFORM_DRIVER_END platform-msi: Export symbol platform_msi_create_irq_domain() irqchip/realtek-rtl: use parent interrupts dt-bindings: interrupt-controller: realtek,rtl-intc: require parents irqchip/realtek-rtl: use irq_domain_add_linear() irqchip: Make irqchip_init() usable on pure ACPI systems bcma: gpio: Use generic_handle_irq_safe() gpio: mlxbf2: Use generic_handle_irq_safe() platform/x86: intel_int0002_vgpio: Use generic_handle_irq_safe() ssb: gpio: Use generic_handle_irq_safe() pinctrl: amd: Use generic_handle_irq_safe() ...
| * pinctrl: amd: Use generic_handle_irq_safe()Sebastian Andrzej Siewior2022-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On PREEMPT_RT enabled kernels the demultiplex interrupt handler is force threaded and runs with interrupts enabled. The invocation of generic_handle_domain_irq() with interrupts enabled triggers a lockdep warning due to a non-irq safe lock acquisition. Instead of disabling interrupts on the driver level, use generic_handle_domain_irq_safe(). [ tglx: Split out from combo patch ] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/YnkfWFzvusFFktSt@linutronix.de Link: https://bugzilla.kernel.org/show_bug.cgi?id=215954
* | Merge tag 'pinctrl-v6.1-1' of ↵Linus Torvalds2022-10-1148-764/+6999
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is nothing exciting going on, no core changes, just a few drivers and cleanups. New drivers: - Cypress CY8C95x0 chip pin control support, along with an immediate cleanup - Mediatek MT8188 SoC pin control support - Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin control support - Qualcomm PM7250, PM8450 - Rockchip RV1126 SoC pin control support Improvements: - Fix some missing pins in the Armada 37xx driver - Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP() macro - Fix some GPIO irq_chips to be immutable - Massive Qualcomm device tree binding cleanup, with more to come" * tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits) MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" pinctrl: Create subdirectory for StarFive drivers dt-bindings: pinctrl: st,stm32: Document interrupt-controller property dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property dt-bindings: pinctrl: st,stm32: Document gpio-line-names pinctrl: st: stop abusing of_get_named_gpio() pinctrl: wpcm450: Correct the fwnode_irq_get() return value check pinctrl: bcm: Remove unused struct bcm6328_pingroup pinctrl: qcom: restrict drivers per ARM/ARM64 pinctrl: bcm: ns: Remove redundant dev_err call gpio: rockchip: request GPIO mux to pinctrl when setting direction pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops pinctrl: cy8c95x0: Drop atomicity on operations on push_pull pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux() pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper pinctrl: stm32: Switch to use dev_err_probe() helper dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings pinctrl: qcom: spmi-gpio: Add compatible for PM7250B ...
| * | pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"Jianlong Huang2022-10-043-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the SoC name to make it more clear. Also the next generation StarFive SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver. No functional change. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220930061404.5418-1-hal.feng@linux.starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: Create subdirectory for StarFive driversJianlong Huang2022-10-045-22/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the StarFive JH7100 pinctrl driver to a new subdirectory in preparation for adding more StarFive pinctrl drivers. No functional change. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> Link: https://lore.kernel.org/r/20220930060819.5320-1-hal.feng@linux.starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: st: stop abusing of_get_named_gpio()Dmitry Torokhov2022-10-041-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin descriptions for this chip only look like standard GPIO device tree descriptions, while in fact they contain additional data (in excess of number of cells specified in description of gpio controllers). They also refer to only pins/gpios belonging to the driver and not to arbitrary gpio in the system. Because we want to stop exporting OF-specific handlers from gpiolib-of, let's parse the pin reference ourself instead of trying to call of_get_named_gpio(). Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/YzSsgoVoJn4+mSpv@google.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: wpcm450: Correct the fwnode_irq_get() return value checkAndy Shevchenko2022-10-041-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fwnode_irq_get() can return zero to indicate IRQ mapping errors. Handle this case by skipping the interrupt resource. Fixes: a1d1e0e3d80a ("pinctrl: nuvoton: Add driver for WPCM450") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20220927175509.15695-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm: Remove unused struct bcm6328_pingroupYuan Can2022-10-041-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit 0e3db16300fb("pinctrl: bcm: Convert drivers to use struct pingroup and PINCTRL_PINGROUP()"), no one use struct bcm6328_pingroup, so remove it. Signed-off-by: Yuan Can <yuancan@huawei.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220927133926.103943-1-yuancan@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: restrict drivers per ARM/ARM64Krzysztof Kozlowski2022-10-041-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point to allow selecting pin-controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs. There won't be a single image for ARMv7 and ARMv8/9 SoCs, so no features/options are lost. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220925112103.148836-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm: ns: Remove redundant dev_err callShang XiaoJing2022-10-041-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_ioremap_resource() prints error message in itself. Remove the dev_err call to avoid redundant error message. Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Ray Jui <ray.jui@broadcom.com> Link: https://lore.kernel.org/r/20220923101038.18036-1-shangxiaojing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: rockchip: add pinmux_ops.gpio_set_direction callbackQuentin Schulz2022-10-041-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the split of gpio and pinctrl sections in their own driver, rockchip_set_mux was called in pinmux_ops.gpio_set_direction for configuring a pin in its GPIO function. This is essential for cases where pinctrl is "bypassed" by gpio consumers otherwise the GPIO function is not configured for the pin and it does not work. Such was the case for the sysfs/libgpiod userspace GPIO handling. Let's re-implement the pinmux_ops.gpio_set_direction callback so that the gpio subsystem can request from the pinctrl driver to put the pin in its GPIO function. Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes") Cc: stable@vger.kernel.org Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20220930132033.4003377-2-foss+kernel@0leil.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxopsAndy Shevchenko2022-09-201-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Align the function names in the cy8c95x0_pmxops() to follow the struct pinmux_ops members naming schema. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220916205450.86278-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: cy8c95x0: Drop atomicity on operations on push_pullAndy Shevchenko2022-09-201-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The push_pull member is always accessed under the mutex, hence no need to use atomic operations on it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220916205450.86278-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux()Andy Shevchenko2022-09-201-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that cy8c95x0_set_mux() missed serialization of IO access. And its implementation looks half-baked. Add locking to the function. Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220916205450.86278-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helperYang Yingliang2022-09-201-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and and prints the error name. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220917122208.1894769-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: stm32: Switch to use dev_err_probe() helperYang Yingliang2022-09-201-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220917122015.1893880-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: spmi-gpio: Add compatible for PM7250BJishnu Prakash2022-09-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for qcom,pm7250b-gpio variant. Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by: David Collins <quic_collinsd@quicinc.com> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220912210624.4527-4-quic_amelende@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: spmi-gpio: Fix the GPIO strength mappingAnjelique Melendez2022-09-191-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | The SPMI based PMICs have the HIGH and LOW GPIO output strength mappings interchanged, fix them. Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> Link: https://lore.kernel.org/r/20220912210624.4527-3-quic_amelende@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: spmi-gpio: add support for LV_VIN2 and MV_VIN3 subtypesDavid Collins2022-09-191-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SPMI PMIC GPIO subtypes GPIO_LV_VIN2 and GPIO_MV_VIN3. GPIO_LV_VIN2 GPIOs support two input reference voltages: VIN0 and VIN1. These are typically connected to 1.8 V and 1.2 V supplies respectively. GPIO_MV_VIN3 GPIOs support three input reference voltages: VIN0, VIN1, and VIN2. These are typically connected to Vph, 1.8 V, and 1.2 V supplies respectively. Signed-off-by: David Collins <quic_collinsd@quicinc.com> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> Link: https://lore.kernel.org/r/20220912210624.4527-2-quic_amelende@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nomadik: remove dead code after DB8540 pinctrl removalLukas Bulwahn2022-09-192-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b6d09f780761 ("pinctrl: nomadik: Drop U8540/9540 support") removes the DB8540 pin controller driver and its config PINCTRL_DB8540. There is some code left-over in the generic nomadik pinctrl driver, i.e., drivers/pinctrl/nomadik/pinctrl-nomadik.{ch}, that is still around for the removed DB8540 pin controller driver. Remove this remaining dead code. This issue was discovered with ./scripts/checkkconfigsymbols.py. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220919065435.27747-1-lukas.bulwahn@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nomadik: Make gpio irqchip immutableLinus Walleij2022-09-191-24/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the Nomadik GPIO irqchip immutable. Tested on the Samsung Galaxy SIII mini GT-I8190. Cc: Marc Zyngier <maz@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220917203036.167607-2-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nomadik: Dereference gpio_chip properlyLinus Walleij2022-09-191-18/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The irq data passed to irc_chip handlers i the struct gpio_chip and nothing else. We are just lucky that the nomadik chip pointer is first in the struct. Use the proper dereferencing and helpers. Reported-by: Marc Zyngier <maz@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220917203036.167607-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'samsung-pinctrl-6.1' of ↵Linus Walleij2022-09-141-4/+4
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.1 1. Minor fix in order of initializing pinctrl driver - GPIOs should be configured before registering gpiolib. 2. Final steps to deprecated bindings headers with register constants. The constants were moved to include files in DTS directories, because these are not suitable for bindings. Remove final references and mark binding header as deprecated to warn any users.
| | * | pinctrl: samsung: Finish initializing the gpios before registering themSaravana Kannan2022-08-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As soon as a gpio is registered, it should be usable by a consumer. So, do all the initialization before registering the gpios. Without this change, a consumer can request a GPIO IRQ and have the gpio to IRQ mapping fail. Signed-off-by: Saravana Kannan <saravanak@google.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Tested-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220727013349.3056826-1-saravanak@google.com
| * | | pinctrl: ocelot: add help and description information to ocelot pinctrl kconfigColin Foster2022-09-142-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missed help information and module export name to the Microsemi Ocelot and Jaguar2 SoC. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Link: https://lore.kernel.org/r/20220909153802.3370088-1-colin.foster@in-advantage.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Use 'default' in all switch-cases (part 2)Andy Shevchenko2022-09-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the default values to the 'default' case in the switches. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220908142134.59068-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: pistachio: Correct the fwnode_irq_get() return value checkAndy Shevchenko2022-09-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fwnode_irq_get() may return all possible signed values, such as Linux error code or 0. Fix the code to handle this properly. Fixes: 1074e1d23a5c ("pinctrl: pistachio: Switch to use fwnode instead of") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220908094323.31965-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: qcom: spmi-gpio: Make irqchip immutableManivannan Sadhasivam2022-09-081-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The irqchip implementation used inside the gpiochips are not supposed to be changed during runtime. So let's make the one inside the spmi-gpio gpiochip immutable. This fixes the below warning during boot: gpio gpiochip0: (c440000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it! Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20220830092232.168561-1-manivannan.sadhasivam@linaro.org [switched two lines as indicated by Johan] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: meson: Switch to use fwnode instead of of_nodeAndy Shevchenko2022-09-082-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220905180034.73132-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: microchip-sgpio: Correct the fwnode_irq_get() return value checkAndy Shevchenko2022-09-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fwnode_irq_get() may return all possible signed values, such as Linux error code. Fix the code to handle this properly. Fixes: be2dc859abd4 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220906115021.8661-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: ingenic: Switch to use fwnode instead of of_nodeAndy Shevchenko2022-09-081-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220905185102.74056-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: imx8m: kconfig: Fix build error on test compileFrancesco Dolcini2022-09-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PINCTRL_IMX depends on OF, however the dependency is missed when selected by PINCTRL_IMX8M* (it does not follow the indirect 'select' statements), select it explicitly. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Linus Walleij <linus.walleij@linaro.org> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/all/202209050605.fezJUgFH-lkp@intel.com/ Fixes: 87c2a29a6bf1 ("pinctrl: imx8m: kconfig: Depends on SOC_IMX8M") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Link: https://lore.kernel.org/r/20220905224408.346425-1-francesco.dolcini@toradex.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Correct comment styleAndy Shevchenko2022-09-081-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a few comments the style is not aligned with the rest. Correct them. While at it, drop unneeded blank lines and deduplicate 'Author'. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-17-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: use bits.h macros for all masksAndy Shevchenko2022-09-081-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of the GENMASK() (far less error-prone, far more concise). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-16-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Override IRQ for one of the expanders on Galileo Gen 1Andy Shevchenko2022-09-081-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACPI table on Intel Galileo Gen 1 has wrong pin number for IRQ resource of the I²C GPIO expander. Since we know what that number is and luckily have GPIO bases fixed for SoC's controllers, we may use a simple DMI quirk to match the platform and retrieve GpioInt() pin on it for the expander in question. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-15-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: support ACPI device found on Galileo Gen1Andy Shevchenko2022-09-081-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of the expander found on Intel Galileo Gen1 board. The platform information comes from ACPI. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-14-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Make use of device propertiesAndy Shevchenko2022-09-082-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Add mod_devicetable.h include. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-13-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Implement ->pin_dbg_show()Andy Shevchenko2022-09-081-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The introduced callback ->pin_dbg_show() is useful for debugging. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-12-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Use 'default' in all switch-casesAndy Shevchenko2022-09-081-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the default values to the 'default' case in the switches. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-11-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Remove custom ->set_config()Andy Shevchenko2022-09-081-25/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have pin configuration getter and setter provided, there is no need to duplicate that in the custom ->set_config(). Instead, switch to gpiochip_generic_config(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-10-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Remove useless conditionalsAndy Shevchenko2022-09-081-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin control framework checks pin boundaries before calling the respective driver's callbacks. Hence no need to check for pin boundaries, the respective conditionals won't be ever true. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-9-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Remove device initializationAndy Shevchenko2022-09-081-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cypress CY8C95x0 chips have an internal EEPROM that defines initial configuration. It might be that bootloader or other entity wrote the platform related setup into it. Don't override it in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-8-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Enable GPIO rangeAndy Shevchenko2022-09-081-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since it's a pin control, GPIO counterpart needs to know the mapping between pin numbering and GPIO numbering. Enable this by calling gpiochip_add_pin_range() at the chip addition time. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-7-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Drop unneeded npins assignmentAndy Shevchenko2022-09-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The npins field is assigned twice. Remove the first occurrence. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Fix pin control name to enable more than oneAndy Shevchenko2022-09-081-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cypress GPIO expander is an I²C discrete component. Hence the platform may contain more than one of a such. Currently this has limitations in the driver due to same name used for all chips of a type. Replace this with device instance specific name. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Fix return value in cy8c95x0_detect()Andy Shevchenko2022-09-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's an obvious typo in never tested piece of code that successful detection shouldn't fail. Fix that. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: Allow IRQ chip core to handle numberingAndy Shevchenko2022-09-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to assign first line number for IRQ chip. Let IRQ core to decide. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: cy8c95x0: make irq_chip immutableAndy Shevchenko2022-09-081-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20220902182650.83098-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: berlin: fix spelling typo in commentJiangshan Yi2022-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix spelling typo in comment. Reported-by: k2ci <kernel-bot@kylinos.cn> Signed-off-by: Jiangshan Yi <yijiangshan@kylinos.cn> Link: https://lore.kernel.org/r/20220905071300.1832105-1-13667453960@163.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: pistachio: Switch to use fwnode instead ofAndy Shevchenko2022-09-031-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220831135512.78407-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit (git 2.34.1) at 2025-02-24 12:10:31 +0000