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* irqchip/stm32-exti: Add all LP timer exti direct events supportFabrice Gasnier2020-10-251-0/+4
| | | | | | | | | Add all remaining LP timer exti direct events, e.g. for LP Timer 2 to 5. LP timer 1 is already listed (e.g. exti 47). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1602859219-15684-2-git-send-email-fabrice.gasnier@st.com
* irqchip/bcm2836: Fix missing __init annotationMarc Zyngier2020-10-251-1/+1
| | | | | | | | bcm2836_arm_irqchip_smp_init() calls set_smp_ipi_range(), which has an __init annotation. Make sure the caller has the same annotation. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
* irqchip/mips: Drop selection of IRQ_DOMAIN_HIERARCHYMarc Zyngier2020-10-161-2/+0
| | | | | | | | | Now that GENERIC_IRQ_IPI selects IRQ_DOMAIN_HIERARCHY, there is no need to have this conditional select for IRQ_MIPS_CPU. Similarily, MIPS_GIC only needs selecting GENERIC_IRQ_IPI. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
* irqchip/mst: Make mst_intc_of_init staticMarc Zyngier2020-10-151-2/+2
| | | | | | | mst_intc_of_init has no external caller, so let's make it static. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
* irqchip/mst: MST_IRQ should depend on ARCH_MEDIATEK or ARCH_MSTARV7Geert Uytterhoeven2020-10-151-0/+1
| | | | | | | | | | | | | | The MStar interrupt controller is only found on MStar, SigmaStar, and Mediatek SoCs. Hence add dependencies on ARCH_MEDIATEK and ARCH_MSTARV7, to prevent asking the user about the MStar interrupt controller driver when configuring a kernel without support for MStar, SigmaStar, and Mediatek SoCs. Fixes: ad4c938c92af9130 ("irqchip/irq-mst: Add MStar interrupt controller support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Daniel Palmer <daniel@thingy.jp> Link: https://lore.kernel.org/r/20201014131703.18021-1-geert+renesas@glider.be
* Merge branch 'irq/mstar' into irq/irqchip-nextMarc Zyngier2020-10-103-0/+208
|\ | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * irqchip/irq-mst: Add MStar interrupt controller supportMark-PK Tsai2020-10-103-0/+208
| | | | | | | | | | | | | | | | | | | | Add MStar interrupt controller support using hierarchy irq domain. Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Daniel Palmer <daniel@thingy.jp> Link: https://lore.kernel.org/r/20200902063344.1852-2-mark-pk.tsai@mediatek.com
* | Merge branch 'irq/irqchip-fixes' into irq/irqchip-nextMarc Zyngier2020-10-103-6/+6
|\ \ | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/loongson-htvec: Fix initial interrupt clearingHuacai Chen2020-09-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In htvec_reset() only the first group of initial interrupts is cleared. This sometimes causes spurious interrupts, so let's clear all groups. While at it, fix the nearby comment that to match the reality of what the driver does. Fixes: 818e915fbac518e8c78e1877 ("irqchip: Add Loongson HyperTransport Vector support") Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1599819978-13999-2-git-send-email-chenhc@lemote.com
| * | irqchip/ti-sci-intr: Fix unsigned comparison to zeroYueHaibing2020-09-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ti_sci_intr_xlate_irq() return -ENOENT on fail, p_hwirq should be int type. Fixes: a5b659bd4bc7 ("irqchip/ti-sci-intr: Add support for INTR being a parent to INTR") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200826035321.18620-1-yuehaibing@huawei.com
| * | irqchip/ti-sci-inta: Fix unsigned comparison to zeroYueHaibing2020-09-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ti_sci_inta_xlate_irq() return -ENOENT on fail, p_hwirq should be int type. Fixes: 5c4b585d2910 ("irqchip/ti-sci-inta: Add support for INTA directly connecting to GIC") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200826035430.21060-1-yuehaibing@huawei.com
* | | Merge branch 'irq/tegra-pmc' into irq/irqchip-nextMarc Zyngier2020-10-102-54/+52
|\ \ \ | | | | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | soc/tegra: pmc: Don't create fake interrupt hierarchy levelsMarc Zyngier2020-10-101-48/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra PMC driver does ungodly things with the interrupt hierarchy, repeatedly corrupting it by pulling hwirq numbers out of thin air, overriding existing IRQ mappings and changing the handling flow of unsuspecting users. All of this is done in the name of preserving the interrupt hierarchy even when these levels do not exist in the HW. Together with the use of proper IRQs for IPIs, this leads to an unbootable system as the rescheduling IPI gets repeatedly repurposed for random drivers... Instead, let's simply mark the level from which the hierarchy does not make sense for the HW, and let the core code trim the usused levels from the hierarchy. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | soc/tegra: pmc: Allow optional irq parent callbacksMarc Zyngier2020-10-101-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the PMC driver resistent to variable depth interrupt hierarchy, which we are about to introduce. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | gpio: tegra186: Allow optional irq parent callbacksMarc Zyngier2020-10-101-2/+13
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Make the tegra186 GPIO driver resistent to variable depth interrupt hierarchy, which we are about to introduce. No functionnal change yet. Signed-off-by: Marc Zyngier <maz@kernel.org>
* | | Merge branch 'irq/qcom-pdc-wakeup' into irq/irqchip-nextMarc Zyngier2020-10-062-7/+18
|\ \ \ | | | | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | irqchip/qcom-pdc: Reset PDC interrupts during initMaulik Shah2020-10-061-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kexec can directly boot into a new kernel without going to complete reboot. This can leave the previous kernel's configuration for PDC interrupts as is. Clear previous kernel's configuration during init by setting interrupts in enable bank to zero. The IRQs specified in qcom,pdc-ranges property are the only ones that can be used by the new kernel so clear only those IRQs. The remaining ones may be in use by a different kernel and should not be set by new kernel. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-7-git-send-email-mkshah@codeaurora.org
| * | | irqchip/qcom-pdc: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flagMaulik Shah2020-10-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the wakeirqs during suspend entry. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-6-git-send-email-mkshah@codeaurora.org
| * | | pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flagMaulik Shah2020-10-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the wakeirqs during suspend entry. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-5-git-send-email-mkshah@codeaurora.org
| * | | pinctrl: qcom: Use return value from irq_set_wake() callMaulik Shah2020-10-061-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | msmgpio irqchip was not using return value of irq_set_irq_wake() callback since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor it implemented .irq_set_wake callback. This lead to irq_set_irq_wake() return error -ENXIO. However from 'commit 4110b5cbb014 ("irqchip/gic-v3: Allow interrupt to be configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE flag. Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent() instead of always returning success. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-3-git-send-email-mkshah@codeaurora.org
| * | | pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flagsMaulik Shah2020-10-061-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked during suspend or during setting irq type since genirq checks irqchip flag of msmgpio irqchip which forwards these calls to its parent PDC irqchip. Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during suspend and mask before setting irq type. Masking before changing type make sures any spurious interrupt is not detected during this operation. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-2-git-send-email-mkshah@codeaurora.org
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*---. \ \ Merge branch 'irq/ipi-as-irq', remote-tracking branches 'origin/irq/dw' and ↵Marc Zyngier2020-09-284-12/+431
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'origin/irq/owl' into irq/irqchip-next Signed-off-by: Marc Zyngier <maz@kernel.org>
| | * | | | irqchip: Add Actions Semi Owl SIRQ controllerCristian Ciocaltea2020-09-252-0/+360
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700 and S900) and provides support for handling up to 3 external interrupt lines. Each line can be independently configured as interrupt and triggers on either of the edges or either of the levels. Additionally, each line can also be masked individually. Co-developed-by: Parthiban Nallathambi <pn@denx.de> Co-developed-by: Saravanan Sekar <sravanhome@gmail.com> Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1a010ef0eb78831b5657d74a0fcdef7a8efb2ec4.1600114378.git.cristian.ciocaltea@gmail.com
| * | | | irqchip/dw-apb-ictl: Add primary interrupt controller supportZhen Lei2020-09-252-9/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> [maz: minor fixups] Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Haoyu Lv <lvhaoyu@huawei.com> Link: https://lore.kernel.org/r/20200924071754.4509-4-thunder.leizhen@huawei.com
| * | | | irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domainsZhen Lei2020-09-251-8/+11
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the required abstractions that will help introducing hierarchical domain support to the dw-apb-ictl driver. No functional change. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> [maz: commit message, some cleanups] Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Haoyu Lv <lvhaoyu@huawei.com> Link: https://lore.kernel.org/r/20200924071754.4509-3-thunder.leizhen@huawei.com
* | | | Merge remote-tracking branch 'origin/irq/gic-retrigger' into irq/irqchip-nextMarc Zyngier2020-09-173-2/+28
|\ \ \ \ | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic-v2, v3: Prevent SW resends entirelyValentin Schneider2020-09-062-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC irqchips can now use a HW resend when a retrigger is invoked by check_irq_resend(). However, should the HW resend fail, check_irq_resend() will still attempt to trigger a SW resend, which is still a bad idea for the GICs. Prevent this from happening by setting IRQD_HANDLE_ENFORCE_IRQCTX on all GIC IRQs. Technically per-cpu IRQs do not need this, as their flow handlers never set IRQS_PENDING, but this aligns all IRQs wrt context enforcement: this also forces all GIC IRQ handling to happen in IRQ context (as defined by in_irq()). Signed-off-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200730170321.31228-3-valentin.schneider@arm.com
| * | | | irqchip/git-v3-its: Implement irq_retrigger callback for device-triggered LPIsMarc Zyngier2020-09-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is pretty easy to provide a retrigger callback for the ITS, as it we already have the required support in terms of irq_set_irqchip_state(). Note that this only works for device-generated LPIs, and not the GICv4 doorbells, which should never have to be retriggered anyway. Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic-v2, v3: Implement irq_chip->irq_retrigger()Valentin Schneider2020-09-062-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While digging around IRQCHIP_EOI_IF_HANDLED and irq/resend.c, it has come to my attention that the IRQ resend situation seems a bit precarious for the GIC(s). When marking an IRQ with IRQS_PENDING, handle_fasteoi_irq() will bail out and issue an irq_eoi(). Should the IRQ in question be re-enabled, check_irq_resend() will trigger a SW resend, which will go through the flow handler again and issue *another* irq_eoi() on the *same* IRQ activation. This is something the GIC spec clearly describes as a bad idea: any EOI must match a previous ACK. Implement irq_chip.irq_retrigger() for the GIC chips by setting the GIC pending bit of the relevant IRQ. After being called by check_irq_resend(), this will eventually trigger a *new* interrupt which we will handle as usual. Signed-off-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200730170321.31228-2-valentin.schneider@arm.com
* | | | | Merge remote-tracking branch 'origin/irq/ipi-as-irq' into irq/irqchip-nextMarc Zyngier2020-09-176-312/+548
|\ \ \ \ \ | | |_|/ / | |/| | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic: Cleanup Franken-GIC handlingMarc Zyngier2020-09-171-29/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a static key identifying Samsung's unique creation, allowing to replace the indirect call to compute the base addresses with a simple test on the static key. Faster, cheaper, negative diffstat. Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/bcm2836: Provide mask/unmask dummy methods for IPIsMarc Zyngier2020-09-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although it doesn't seem possible to disable individual mailbox interrupts, we still need to provide some callbacks. Fixes: 09eb672ce4fb ("irqchip/bcm2836: Configure mailbox interrupts as standard interrupts") Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/armada-370-xp: Configure IPIs as standard interruptsMarc Zyngier2020-09-171-84/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To introduce IPIs as standard interrupts to the Armada 370-XP driver, let's allocate a completely separate irqdomain and irqchip combo that lives parallel to the "standard" one. This effectively should be modelled as a chained interrupt controller, but the code is in such a state that it is pretty hard to shoehorn, as it would require the rewrite of the MSI layer as well. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/hip04: Configure IPIs as standard interruptsMarc Zyngier2020-09-171-49/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to switch the hip04 driver to provide standard interrupts for IPIs, rework the way interrupts are allocated, making sure the irqdomain covers the SGIs as well as the rest of the interrupt range. The driver is otherwise so old-school that it creates all interrupts upfront (duh!), so there is hardly anything else to change, apart from communicating the IPIs to the arch code. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/bcm2836: Configure mailbox interrupts as standard interruptsMarc Zyngier2020-09-171-26/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to switch the bcm2836 driver to privide standard interrupts for IPIs, it first needs to stop lying about the way things work. The mailbox interrupt is actually a multiplexer, with enough bits to store 32 pending interrupts per CPU. So let's turn it into a chained irqchip. Once this is done, we can instanciate the corresponding IPIs, and pass them to the architecture code. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic-common: Don't enable SGIs by defaultMarc Zyngier2020-09-171-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture code now enables the IPIs as required, so no need to enable SGIs by default in the GIC code. Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic: Configure SGIs as standard interruptsMarc Zyngier2020-09-171-41/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the way we deal with GIC SGIs by turning them into proper IRQs, and calling into the arch code to register the interrupt range instead of a callback. Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic: Refactor SMP configurationMarc Zyngier2020-09-171-36/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we are about to change quite a lot of the SMP support code, let's start by moving it around so that it minimizes the amount of #ifdefery. Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic-v3: Configure SGIs as standard interruptsMarc Zyngier2020-09-171-43/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the way we deal with GICv3 SGIs by turning them into proper IRQs, and calling into the arch code to register the interrupt range instead of a callback. Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic-v3: Describe the SGI rangeMarc Zyngier2020-09-131-3/+15
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | As we are about to start making use of SGIs in a more conventional way, let's describe it is the GICv3 list of interrupt types. Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
* | | | Merge remote-tracking branch 'origin/irq/gic-v3-nmi-ns' into irq/irqchip-nextMarc Zyngier2020-09-171-14/+46
|\ \ \ \ | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/gic-v3: Support pseudo-NMIs when SCR_EL3.FIQ == 0Alexandru Elisei2020-09-131-12/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC's internal view of the priority mask register and the assigned interrupt priorities are based on whether GIC security is enabled and whether firmware routes Group 0 interrupts to EL3. At the moment, we support priority masking when ICC_PMR_EL1 and interrupt priorities are either both modified by the GIC, or both left unchanged. Trusted Firmware-A's default interrupt routing model allows Group 0 interrupts to be delivered to the non-secure world (SCR_EL3.FIQ == 0). Unfortunately, this is precisely the case that the GIC driver doesn't support: ICC_PMR_EL1 remains unchanged, but the GIC's view of interrupt priorities is different from the software programmed values. Support pseudo-NMIs when SCR_EL3.FIQ == 0 by using a different value to mask regular interrupts. All the other values remain the same. Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200912153707.667731-3-alexandru.elisei@arm.com
| * | | | irqchip/gic-v3: Spell out when pseudo-NMIs are enabledAlexandru Elisei2020-09-131-2/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When NMIs cannot be enabled, the driver prints a message stating that unambiguously. When they are enabled, the only feedback we get is a message regarding the use of synchronization for ICC_PMR_EL1 writes, which is not as useful for a user who is not intimately familiar with how NMIs are implemented. Let's make it obvious that pseudo-NMIs are enabled. Keep the message about using a barrier for ICC_PMR_EL1 writes, because it has a non-negligible impact on performance. Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200912153707.667731-2-alexandru.elisei@arm.com
* | | | Merge remote-tracking branch 'origin/irq/dev_err_probe' into irq/irqchip-nextMarc Zyngier2020-09-174-26/+12
|\ \ \ \ | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip/imx-irqsteer: Use dev_err_probe() to simplify error handlingAnson Huang2020-09-131-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_err_probe() can reduce code size, uniform error handling and record the defer probe reason etc., use it to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1597126576-18383-2-git-send-email-Anson.Huang@nxp.com
| * | | | irqchip/imx-intmux: Use dev_err_probe() to simplify error handlingAnson Huang2020-09-131-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_err_probe() can reduce code size, uniform error handling and record the defer probe reason etc., use it to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1597126576-18383-1-git-send-email-Anson.Huang@nxp.com
| * | | | irqchip/ti-sci: Simplify with dev_err_probe()Krzysztof Kozlowski2020-09-132-14/+6
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. There is also no need to assign NULL to 'intr->sci' as it is part of devm-allocated memory. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200902174615.24695-1-krzk@kernel.org
* | | | Merge remote-tracking branch 'origin/irq/misc-5.10' into irq/irqchip-nextMarc Zyngier2020-09-171-2/+2
|\ \ \ \ | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | | | irqchip: Kconfig: Update description for RENESAS_IRQC configLad Prabhakar2020-09-131-2/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | irq-renesas-irqc driver is also used on Renesas RZ/G{1,2} SoC's, update the same to reflect the description for RENESAS_IRQC config. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200911100439.19878-1-prabhakar.mahadev-lad.rj@bp.renesas.com
* | | | irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCsSuman Anna2020-09-172-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The PRUSS INTC present within the ICSSG supports more System Events (160 vs 64), more Interrupt Channels and Host Interrupts (20 vs 10) compared to the previous generation PRUSS INTC instances. The first 2 and the last 10 of these host interrupt lines are used by the PRU and other auxiliary cores and sub-modules within the ICSSG, with 8 host interrupts connected to MPU. The host interrupts 5, 6, 7 are also connected to the other ICSSG instances within the SoC and can be partitioned as per system integration through the board dts files. Enhance the PRUSS INTC driver to add support for this ICSSG INTC instance. Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
generated by cgit (git 2.34.1) at 2025-02-25 01:07:49 +0000