From 91276c0fa4b405c90d7a7fafdca84ae18a516bbf Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 2 Apr 2022 12:29:36 +0200 Subject: ARM: s3c24xx: remove support for ISA drivers on BAST PC/104 BAST is the one machine that theoretically supports unmodified ISA drivers for hardware on its PC/104 connector, using a custom version of the inb()/outb() and inw()/outw() macros. This is incompatible with the generic version used in asm/io.h, and can't easily be used in a multiplatform kernel. Removing the special case for 16-bit I/O port access on BAST gets us closer to multiplatform, at the expense of any PC/104 users with 16-bit cards having to either use an older kernel or modify their ISA drivers to manually ioremap() the area and use readw()/write() in place of inw()/outw(). Either way is probably ok, given that there is a recurring discussion about dropping s3c24xx altogether, and many traditional ISA drivers are already gone. Machines other than BAST already have no support for ISA drivers, though a couple of them do map one of the external chip-selects into the ISA port range, using the same address for 8-bit and 16-bit I/O. It is unlikely that anything actually uses this mapping, but it's also easy to keep this working by mapping it to the normal platform-independent PCI I/O base that is otherwise unused on s3c24xx. The mach/map-base.h file is no longer referenced in global headers and can be moved into the platform directory. Acked-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/mach-s3c/Kconfig.s3c24xx | 1 - arch/arm/mach-s3c/cpu.c | 2 +- arch/arm/mach-s3c/include/mach/io-s3c24xx.h | 50 ----------------------------- arch/arm/mach-s3c/include/mach/io.h | 8 ----- arch/arm/mach-s3c/include/mach/map-base.h | 42 ------------------------ arch/arm/mach-s3c/irq-pm-s3c24xx.c | 2 +- arch/arm/mach-s3c/mach-anubis.c | 5 --- arch/arm/mach-s3c/mach-bast.c | 5 --- arch/arm/mach-s3c/mach-osiris.c | 5 --- arch/arm/mach-s3c/mach-rx3715.c | 6 ---- arch/arm/mach-s3c/mach-smdk2416.c | 10 ------ arch/arm/mach-s3c/mach-smdk2440.c | 10 ------ arch/arm/mach-s3c/mach-smdk2443.c | 10 ------ arch/arm/mach-s3c/mach-vr1000.c | 5 --- arch/arm/mach-s3c/map-base.h | 48 +++++++++++++++++++++++++++ arch/arm/mach-s3c/map-s3c24xx.h | 2 +- arch/arm/mach-s3c/map-s3c64xx.h | 2 +- 17 files changed, 52 insertions(+), 161 deletions(-) delete mode 100644 arch/arm/mach-s3c/include/mach/io-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/io.h delete mode 100644 arch/arm/mach-s3c/include/mach/map-base.h create mode 100644 arch/arm/mach-s3c/map-base.h (limited to 'arch/arm/mach-s3c') diff --git a/arch/arm/mach-s3c/Kconfig.s3c24xx b/arch/arm/mach-s3c/Kconfig.s3c24xx index 000e3e234f71..d47df6427e89 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c24xx +++ b/arch/arm/mach-s3c/Kconfig.s3c24xx @@ -181,7 +181,6 @@ config MACH_AML_M5900 config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" - select ISA select MACH_BAST_IDE select S3C2410_COMMON_DCLK select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ diff --git a/arch/arm/mach-s3c/cpu.c b/arch/arm/mach-s3c/cpu.c index 6e9772555f0d..05a6b4be1768 100644 --- a/arch/arm/mach-s3c/cpu.c +++ b/arch/arm/mach-s3c/cpu.c @@ -10,7 +10,7 @@ #include #include -#include +#include "map-base.h" #include "cpu.h" unsigned long samsung_cpu_id; diff --git a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h deleted file mode 100644 index 738b775d3336..000000000000 --- a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-s3c2410/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * (C) 2003 Simtec Electronics -*/ - -#ifndef __ASM_ARM_ARCH_IO_S3C24XX_H -#define __ASM_ARM_ARCH_IO_S3C24XX_H - -#include - -/* - * ISA style IO, for each machine to sort out mappings for, - * if it implements it. We reserve two 16M regions for ISA, - * so the PC/104 can use separate addresses for 8-bit and - * 16-bit port I/O. - */ -#define PCIO_BASE S3C_ADDR(0x02000000) -#define IO_SPACE_LIMIT 0x00ffffff -#define S3C24XX_VA_ISA_WORD (PCIO_BASE) -#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000) - -#ifdef CONFIG_ISA - -#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p)) -#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p)) -#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p)) - -#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p)) -#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p)) -#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p)) - -#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#else - -#define __io(x) (PCIO_BASE + (x)) - -#endif - -#endif diff --git a/arch/arm/mach-s3c/include/mach/io.h b/arch/arm/mach-s3c/include/mach/io.h deleted file mode 100644 index 30a0135708dc..000000000000 --- a/arch/arm/mach-s3c/include/mach/io.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Krzysztof Kozlowski - */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "io-s3c24xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/map-base.h b/arch/arm/mach-s3c/include/mach/map-base.h deleted file mode 100644 index 34b39ded0e2e..000000000000 --- a/arch/arm/mach-s3c/include/mach/map-base.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2003, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C - Memory map definitions (virtual addresses) - */ - -#ifndef __ASM_PLAT_MAP_H -#define __ASM_PLAT_MAP_H __FILE__ - -/* Fit all our registers in at 0xF6000000 upwards, trying to use as - * little of the VA space as possible so vmalloc and friends have a - * better chance of getting memory. - * - * we try to ensure stuff like the IRQ registers are available for - * an single MOVS instruction (ie, only 8 bits of set data) - */ - -#define S3C_ADDR_BASE 0xF6000000 - -#ifndef __ASSEMBLY__ -#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) -#else -#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) -#endif - -#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ -#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ -#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ -#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ -#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ -#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ - -/* This is used for the CPU specific mappings that may be needed, so that - * they do not need to directly used S3C_ADDR() and thus make it easier to - * modify the space for mapping. - */ -#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) - -#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/mach-s3c/irq-pm-s3c24xx.c b/arch/arm/mach-s3c/irq-pm-s3c24xx.c index 4d5e28312d91..55f41135ad70 100644 --- a/arch/arm/mach-s3c/irq-pm-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-pm-s3c24xx.c @@ -15,7 +15,7 @@ #include "cpu.h" #include "pm.h" -#include +#include "map-base.h" #include "map-s3c.h" #include "regs-irq.h" diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 04147cc0adcc..60df40052209 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -57,11 +57,6 @@ static struct map_desc anubis_iodesc[] __initdata = { .pfn = __phys_to_pfn(0x0), .length = SZ_4M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(0x0), - .length = SZ_4M, - .type = MT_DEVICE, }, /* we could possibly compress the next set down into a set of smaller tables diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index 27e8d5950228..5ac24e406157 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -75,11 +75,6 @@ static struct map_desc bast_iodesc[] __initdata = { .pfn = PA_CS2(BAST_PA_ISAIO), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, }, /* bast CPLD control registers, and external interrupt controls */ { diff --git a/arch/arm/mach-s3c/mach-osiris.c b/arch/arm/mach-s3c/mach-osiris.c index 3aefb9d22340..8387773f4fd4 100644 --- a/arch/arm/mach-s3c/mach-osiris.c +++ b/arch/arm/mach-s3c/mach-osiris.c @@ -58,11 +58,6 @@ static struct map_desc osiris_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C2410_CS5), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS5), - .length = SZ_16M, - .type = MT_DEVICE, }, /* CPLD control registers */ diff --git a/arch/arm/mach-s3c/mach-rx3715.c b/arch/arm/mach-s3c/mach-rx3715.c index 9fd2d9dc3689..586cb0fdfce0 100644 --- a/arch/arm/mach-s3c/mach-rx3715.c +++ b/arch/arm/mach-s3c/mach-rx3715.c @@ -48,13 +48,7 @@ static struct map_desc rx3715_iodesc[] __initdata = { /* dump ISA space somewhere unused */ - { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS3), - .length = SZ_1M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS3), .length = SZ_1M, diff --git a/arch/arm/mach-s3c/mach-smdk2416.c b/arch/arm/mach-s3c/mach-smdk2416.c index 4d883a792cc6..38b4a7cd4178 100644 --- a/arch/arm/mach-s3c/mach-smdk2416.c +++ b/arch/arm/mach-s3c/mach-smdk2416.c @@ -53,16 +53,6 @@ static struct map_desc smdk2416_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-smdk2440.c b/arch/arm/mach-s3c/mach-smdk2440.c index 7f6fe0db04f3..392554b1eba2 100644 --- a/arch/arm/mach-s3c/mach-smdk2440.c +++ b/arch/arm/mach-s3c/mach-smdk2440.c @@ -43,16 +43,6 @@ static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-smdk2443.c b/arch/arm/mach-s3c/mach-smdk2443.c index fc54c91ade56..4c541a03e49e 100644 --- a/arch/arm/mach-s3c/mach-smdk2443.c +++ b/arch/arm/mach-s3c/mach-smdk2443.c @@ -40,16 +40,6 @@ static struct map_desc smdk2443_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-vr1000.c b/arch/arm/mach-s3c/mach-vr1000.c index 5c3d07cf2e79..3aa8c707f8a2 100644 --- a/arch/arm/mach-s3c/mach-vr1000.c +++ b/arch/arm/mach-s3c/mach-vr1000.c @@ -67,11 +67,6 @@ static struct map_desc vr1000_iodesc[] __initdata = { .pfn = PA_CS2(BAST_PA_ISAIO), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, }, /* CPLD control registers, and external interrupt controls */ diff --git a/arch/arm/mach-s3c/map-base.h b/arch/arm/mach-s3c/map-base.h new file mode 100644 index 000000000000..463a995b399b --- /dev/null +++ b/arch/arm/mach-s3c/map-base.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C - Memory map definitions (virtual addresses) + */ + +#ifndef __ASM_PLAT_MAP_H +#define __ASM_PLAT_MAP_H __FILE__ + +/* Fit all our registers in at 0xF6000000 upwards, trying to use as + * little of the VA space as possible so vmalloc and friends have a + * better chance of getting memory. + * + * we try to ensure stuff like the IRQ registers are available for + * an single MOVS instruction (ie, only 8 bits of set data) + */ + +#define S3C_ADDR_BASE 0xF6000000 + +#ifndef __ASSEMBLY__ +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#else +#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) +#endif + +#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ +#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ +#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ +#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ +#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ + +/* ISA device mapping for BAST to use with inb()/outb() on 8-bit I/O. + * 16-bit I/O on BAST now requires driver modifications to manually + * ioremap CS3. + */ +#define S3C24XX_VA_ISA_BYTE PCI_IOBASE + +/* This is used for the CPU specific mappings that may be needed, so that + * they do not need to directly used S3C_ADDR() and thus make it easier to + * modify the space for mapping. + */ +#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) + +#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/mach-s3c/map-s3c24xx.h b/arch/arm/mach-s3c/map-s3c24xx.h index b5dba78a9dd7..f8d075b11d6f 100644 --- a/arch/arm/mach-s3c/map-s3c24xx.h +++ b/arch/arm/mach-s3c/map-s3c24xx.h @@ -9,7 +9,7 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H -#include +#include "map-base.h" #include "map-s3c.h" /* diff --git a/arch/arm/mach-s3c/map-s3c64xx.h b/arch/arm/mach-s3c/map-s3c64xx.h index d7740d2a77c4..9de1c58bcb06 100644 --- a/arch/arm/mach-s3c/map-s3c64xx.h +++ b/arch/arm/mach-s3c/map-s3c64xx.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H __FILE__ -#include +#include "map-base.h" #include "map-s3c.h" /* -- cgit From c78a41fc04f0209cba1e62ccbe6a4844633515e7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 2 Apr 2022 15:28:18 +0200 Subject: ARM: s3c24xx: convert to sparse-irq As a final bit of preparation for converting to ARCH_MULTIPLATFORM, change the interrupt handling for s3c24xx to use sparse IRQs. Since the number of possible interrupts is already fixed and relatively small per chip, just make it use all legacy interrupts preallocated using the .nr_irqs field in the machine descriptor, rather than actually allocating domains on the fly. Acked-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/mach-s3c/bast-ide.c | 2 +- arch/arm/mach-s3c/bast-irq.c | 2 +- arch/arm/mach-s3c/dev-audio-s3c64xx.c | 2 +- arch/arm/mach-s3c/dev-uart-s3c64xx.c | 2 +- arch/arm/mach-s3c/devs.c | 2 +- arch/arm/mach-s3c/gpio-samsung.c | 2 +- arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h | 213 ------------------------- arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h | 172 -------------------- arch/arm/mach-s3c/include/mach/irqs.h | 9 -- arch/arm/mach-s3c/irq-s3c24xx.c | 2 +- arch/arm/mach-s3c/irqs-s3c24xx.h | 219 ++++++++++++++++++++++++++ arch/arm/mach-s3c/irqs-s3c64xx.h | 172 ++++++++++++++++++++ arch/arm/mach-s3c/irqs.h | 9 ++ arch/arm/mach-s3c/mach-amlm5900.c | 2 + arch/arm/mach-s3c/mach-anubis.c | 1 + arch/arm/mach-s3c/mach-anw6410.c | 2 +- arch/arm/mach-s3c/mach-at2440evb.c | 1 + arch/arm/mach-s3c/mach-bast.c | 1 + arch/arm/mach-s3c/mach-crag6410-module.c | 2 +- arch/arm/mach-s3c/mach-crag6410.c | 2 +- arch/arm/mach-s3c/mach-gta02.c | 1 + arch/arm/mach-s3c/mach-h1940.c | 1 + arch/arm/mach-s3c/mach-hmt.c | 2 +- arch/arm/mach-s3c/mach-jive.c | 2 +- arch/arm/mach-s3c/mach-mini2440.c | 3 +- arch/arm/mach-s3c/mach-mini6410.c | 2 +- arch/arm/mach-s3c/mach-n30.c | 2 + arch/arm/mach-s3c/mach-ncp.c | 2 +- arch/arm/mach-s3c/mach-nexcoder.c | 1 + arch/arm/mach-s3c/mach-osiris.c | 1 + arch/arm/mach-s3c/mach-otom.c | 1 + arch/arm/mach-s3c/mach-qt2410.c | 1 + arch/arm/mach-s3c/mach-real6410.c | 2 +- arch/arm/mach-s3c/mach-rx1950.c | 1 + arch/arm/mach-s3c/mach-rx3715.c | 1 + arch/arm/mach-s3c/mach-smartq5.c | 2 +- arch/arm/mach-s3c/mach-smartq7.c | 2 +- arch/arm/mach-s3c/mach-smdk2410.c | 1 + arch/arm/mach-s3c/mach-smdk2413.c | 3 + arch/arm/mach-s3c/mach-smdk2416.c | 1 + arch/arm/mach-s3c/mach-smdk2440.c | 1 + arch/arm/mach-s3c/mach-smdk2443.c | 2 +- arch/arm/mach-s3c/mach-smdk6400.c | 2 +- arch/arm/mach-s3c/mach-smdk6410.c | 2 +- arch/arm/mach-s3c/mach-tct_hammer.c | 1 + arch/arm/mach-s3c/mach-vr1000.c | 1 + arch/arm/mach-s3c/mach-vstms.c | 1 + arch/arm/mach-s3c/pl080.c | 2 +- arch/arm/mach-s3c/pm-core-s3c24xx.h | 2 +- arch/arm/mach-s3c/pm-s3c2412.c | 2 +- arch/arm/mach-s3c/pm-s3c64xx.c | 2 +- arch/arm/mach-s3c/pm.c | 2 +- arch/arm/mach-s3c/s3c2443.c | 2 +- arch/arm/mach-s3c/s3c24xx.h | 2 +- arch/arm/mach-s3c/s3c64xx.c | 2 +- arch/arm/mach-s3c/simtec-usb.c | 2 +- 56 files changed, 455 insertions(+), 424 deletions(-) delete mode 100644 arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/irqs.h create mode 100644 arch/arm/mach-s3c/irqs-s3c24xx.h create mode 100644 arch/arm/mach-s3c/irqs-s3c64xx.h create mode 100644 arch/arm/mach-s3c/irqs.h (limited to 'arch/arm/mach-s3c') diff --git a/arch/arm/mach-s3c/bast-ide.c b/arch/arm/mach-s3c/bast-ide.c index da64db1811d8..67f0adc1fec0 100644 --- a/arch/arm/mach-s3c/bast-ide.c +++ b/arch/arm/mach-s3c/bast-ide.c @@ -20,7 +20,7 @@ #include #include "map.h" -#include +#include "irqs.h" #include "bast.h" diff --git a/arch/arm/mach-s3c/bast-irq.c b/arch/arm/mach-s3c/bast-irq.c index d299f124e6dc..cfc2ddc65513 100644 --- a/arch/arm/mach-s3c/bast-irq.c +++ b/arch/arm/mach-s3c/bast-irq.c @@ -16,7 +16,7 @@ #include #include "regs-irq.h" -#include +#include "irqs.h" #include "bast.h" diff --git a/arch/arm/mach-s3c/dev-audio-s3c64xx.c b/arch/arm/mach-s3c/dev-audio-s3c64xx.c index fc2f077afd24..909e82c148ba 100644 --- a/arch/arm/mach-s3c/dev-audio-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-audio-s3c64xx.c @@ -10,7 +10,7 @@ #include #include -#include +#include "irqs.h" #include "map.h" #include "devs.h" diff --git a/arch/arm/mach-s3c/dev-uart-s3c64xx.c b/arch/arm/mach-s3c/dev-uart-s3c64xx.c index 8288e8d6c092..f9c947b8971b 100644 --- a/arch/arm/mach-s3c/dev-uart-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-uart-s3c64xx.c @@ -16,7 +16,7 @@ #include #include #include "map.h" -#include +#include "irqs.h" #include "devs.h" diff --git a/arch/arm/mach-s3c/devs.c b/arch/arm/mach-s3c/devs.c index 1e266fc24f9b..9ac07c023adf 100644 --- a/arch/arm/mach-s3c/devs.c +++ b/arch/arm/mach-s3c/devs.c @@ -38,7 +38,7 @@ #include #include -#include +#include "irqs.h" #include "map.h" #include "gpio-samsung.h" #include "gpio-cfg.h" diff --git a/arch/arm/mach-s3c/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c index fda2c01f5a08..b7fc7c41309c 100644 --- a/arch/arm/mach-s3c/gpio-samsung.c +++ b/arch/arm/mach-s3c/gpio-samsung.c @@ -26,7 +26,7 @@ #include -#include +#include "irqs.h" #include "map.h" #include "regs-gpio.h" #include "gpio-samsung.h" diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h b/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h deleted file mode 100644 index aaf3bae08b52..000000000000 --- a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks - */ - - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - */ - -#define S3C2410_CPUIRQ_OFFSET (16) - -#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) - -/* main cpu interrupts */ -#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ -#define IRQ_EINT1 S3C2410_IRQ(1) -#define IRQ_EINT2 S3C2410_IRQ(2) -#define IRQ_EINT3 S3C2410_IRQ(3) -#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ -#define IRQ_EINT8t23 S3C2410_IRQ(5) -#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ -#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ -#define IRQ_BATT_FLT S3C2410_IRQ(7) -#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ -#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ -#define IRQ_TIMER0 S3C2410_IRQ(10) -#define IRQ_TIMER1 S3C2410_IRQ(11) -#define IRQ_TIMER2 S3C2410_IRQ(12) -#define IRQ_TIMER3 S3C2410_IRQ(13) -#define IRQ_TIMER4 S3C2410_IRQ(14) -#define IRQ_UART2 S3C2410_IRQ(15) -#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ -#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ -#define IRQ_DMA1 S3C2410_IRQ(18) -#define IRQ_DMA2 S3C2410_IRQ(19) -#define IRQ_DMA3 S3C2410_IRQ(20) -#define IRQ_SDI S3C2410_IRQ(21) -#define IRQ_SPI0 S3C2410_IRQ(22) -#define IRQ_UART1 S3C2410_IRQ(23) -#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ -#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ -#define IRQ_USBD S3C2410_IRQ(25) -#define IRQ_USBH S3C2410_IRQ(26) -#define IRQ_IIC S3C2410_IRQ(27) -#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ -#define IRQ_SPI1 S3C2410_IRQ(29) -#define IRQ_RTC S3C2410_IRQ(30) -#define IRQ_ADCPARENT S3C2410_IRQ(31) - -/* interrupts generated from the external interrupts sources */ -#define IRQ_EINT0_2412 S3C2410_IRQ(32) -#define IRQ_EINT1_2412 S3C2410_IRQ(33) -#define IRQ_EINT2_2412 S3C2410_IRQ(34) -#define IRQ_EINT3_2412 S3C2410_IRQ(35) -#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ -#define IRQ_EINT5 S3C2410_IRQ(37) -#define IRQ_EINT6 S3C2410_IRQ(38) -#define IRQ_EINT7 S3C2410_IRQ(39) -#define IRQ_EINT8 S3C2410_IRQ(40) -#define IRQ_EINT9 S3C2410_IRQ(41) -#define IRQ_EINT10 S3C2410_IRQ(42) -#define IRQ_EINT11 S3C2410_IRQ(43) -#define IRQ_EINT12 S3C2410_IRQ(44) -#define IRQ_EINT13 S3C2410_IRQ(45) -#define IRQ_EINT14 S3C2410_IRQ(46) -#define IRQ_EINT15 S3C2410_IRQ(47) -#define IRQ_EINT16 S3C2410_IRQ(48) -#define IRQ_EINT17 S3C2410_IRQ(49) -#define IRQ_EINT18 S3C2410_IRQ(50) -#define IRQ_EINT19 S3C2410_IRQ(51) -#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ -#define IRQ_EINT21 S3C2410_IRQ(53) -#define IRQ_EINT22 S3C2410_IRQ(54) -#define IRQ_EINT23 S3C2410_IRQ(55) - -#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) -#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) - -#define IRQ_LCD_FIFO S3C2410_IRQ(56) -#define IRQ_LCD_FRAME S3C2410_IRQ(57) - -/* IRQs for the interal UARTs, and ADC - * these need to be ordered in number of appearance in the - * SUBSRC mask register -*/ - -#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) - -#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ -#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) -#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) - -#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ -#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) -#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) - -#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ -#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) -#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) - -#define IRQ_TC S3C2410_IRQSUB(9) -#define IRQ_ADC S3C2410_IRQSUB(10) - -/* extra irqs for s3c2412 */ - -#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) - -#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) -#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) - - -#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) -#define IRQ_S3C2416_DMA S3C2410_IRQ(17) -#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) -#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) -#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) - -#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) -#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) -#define IRQ_S32416_WDT S3C2410_IRQSUB(27) -#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) - -/* second interrupt-register of s3c2416/s3c2450 */ - -#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) -#define IRQ_S3C2416_2D S3C2416_IRQ(0) -#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) -#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) -#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3) -#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4) -#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5) -#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6) -#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7) - -/* extra irqs for s3c2440 */ - -#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ -#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ -#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) -#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) - -/* irqs for s3c2443 */ - -#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ -#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ -#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ -#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ -#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ - -#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ - -#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 -#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC - -#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) -#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) - -#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) - -/* UART3 */ -#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) -#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) -#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) - -#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) -#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) - -#if defined(CONFIG_CPU_S3C2416) -#define NR_IRQS (IRQ_S3C2416_I2S1 + 1) -#else -#define NR_IRQS (IRQ_S3C2443_AC97 + 1) -#endif - -/* compatibility define. */ -#define IRQ_UART3 IRQ_S3C2443_UART3 -#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 -#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 -#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 - -#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 -#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 - -#ifdef CONFIG_CPU_S3C2440 -#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 -#else -#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 -#endif - -/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ -#define FIQ_START IRQ_EINT0 - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h b/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h deleted file mode 100644 index c244e480e6b3..000000000000 --- a/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - IRQ support - */ - -#ifndef __ASM_MACH_S3C64XX_IRQS_H -#define __ASM_MACH_S3C64XX_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - * - * note, since we're using the VICs, our start must be a - * mulitple of 32 to allow the common code to work - */ - -#define S3C_IRQ_OFFSET (32) - -#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) - -#define IRQ_VIC0_BASE S3C_IRQ(0) -#define IRQ_VIC1_BASE S3C_IRQ(32) - -/* VIC based IRQs */ - -#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) -#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) - -/* VIC0 */ - -#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) -#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) -#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) -#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) -#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) -#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) -#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) -#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) -#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) -#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) -#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) -#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) -#define IRQ_2D S3C64XX_IRQ_VIC0(11) -#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) -#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) -#define IRQ_BATF S3C64XX_IRQ_VIC0(14) -#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) -#define IRQ_MFC S3C64XX_IRQ_VIC0(16) -#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) -#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) -#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) -#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) -#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) -#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) -#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) -#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) -#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) -#define IRQ_WDT S3C64XX_IRQ_VIC0(26) -#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) -#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) -#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) -#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) -#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) - -/* VIC1 */ - -#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) -#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) -#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) -#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) -#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) -#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) -#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) -#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) -#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) -#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) -#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) -#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) -#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) -#define IRQ_NFC S3C64XX_IRQ_VIC1(13) -#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) -#define IRQ_USBH S3C64XX_IRQ_VIC1(15) -#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) -#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) -#define IRQ_IIC S3C64XX_IRQ_VIC1(18) -#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) -#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) -#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) -#define IRQ_MSM S3C64XX_IRQ_VIC1(22) -#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) -#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) -#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) -#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ -#define IRQ_OTG S3C64XX_IRQ_VIC1(26) -#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) -#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) -#define IRQ_SEC S3C64XX_IRQ_VIC1(29) -#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) -#define IRQ_TC IRQ_PENDN -#define IRQ_ADC S3C64XX_IRQ_VIC1(31) - -/* compatibility for device defines */ - -#define IRQ_IIC1 IRQ_S3C6410_IIC1 - -/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series - * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE - * which we place after the pair of VICs. */ - -#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) - -#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) -#define IRQ_EINT(x) S3C_EINT(x) -#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) - -/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) - * that they are sourced from the GPIO pins but with a different scheme for - * priority and source indication. - * - * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO - * interrupts, but for historical reasons they are kept apart from these - * next interrupts. - * - * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the - * machine specific support files. - */ - -#define IRQ_EINT_GROUP1_NR (15) -#define IRQ_EINT_GROUP2_NR (8) -#define IRQ_EINT_GROUP3_NR (5) -#define IRQ_EINT_GROUP4_NR (14) -#define IRQ_EINT_GROUP5_NR (7) -#define IRQ_EINT_GROUP6_NR (10) -#define IRQ_EINT_GROUP7_NR (16) -#define IRQ_EINT_GROUP8_NR (15) -#define IRQ_EINT_GROUP9_NR (9) - -#define IRQ_EINT_GROUP_BASE S3C_EINT(28) -#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) -#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) -#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) -#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) -#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) -#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) -#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) -#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) -#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) - -#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) - -/* Some boards have their own IRQs behind this */ -#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) - -/* Set the default nr_irqs, boards can override if necessary */ -#define S3C64XX_NR_IRQS IRQ_BOARD_START - -/* Compatibility */ - -#define IRQ_ONENAND IRQ_ONENAND0 -#define IRQ_I2S0 IRQ_S3C6410_IIS - -#endif /* __ASM_MACH_S3C64XX_IRQS_H */ - diff --git a/arch/arm/mach-s3c/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs.h deleted file mode 100644 index 0bff1c1c8eb0..000000000000 --- a/arch/arm/mach-s3c/include/mach/irqs.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "irqs-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "irqs-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 3776d5206f9b..088cc04b7431 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -26,7 +26,7 @@ #include #include -#include +#include "irqs.h" #include "regs-irq.h" #include "regs-gpio.h" diff --git a/arch/arm/mach-s3c/irqs-s3c24xx.h b/arch/arm/mach-s3c/irqs-s3c24xx.h new file mode 100644 index 000000000000..fecbf7e440c6 --- /dev/null +++ b/arch/arm/mach-s3c/irqs-s3c24xx.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks + */ + + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + */ + +#define S3C2410_CPUIRQ_OFFSET (16) + +#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) + +/* main cpu interrupts */ +#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ +#define IRQ_EINT1 S3C2410_IRQ(1) +#define IRQ_EINT2 S3C2410_IRQ(2) +#define IRQ_EINT3 S3C2410_IRQ(3) +#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ +#define IRQ_EINT8t23 S3C2410_IRQ(5) +#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ +#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ +#define IRQ_BATT_FLT S3C2410_IRQ(7) +#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ +#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ +#define IRQ_TIMER0 S3C2410_IRQ(10) +#define IRQ_TIMER1 S3C2410_IRQ(11) +#define IRQ_TIMER2 S3C2410_IRQ(12) +#define IRQ_TIMER3 S3C2410_IRQ(13) +#define IRQ_TIMER4 S3C2410_IRQ(14) +#define IRQ_UART2 S3C2410_IRQ(15) +#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ +#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ +#define IRQ_DMA1 S3C2410_IRQ(18) +#define IRQ_DMA2 S3C2410_IRQ(19) +#define IRQ_DMA3 S3C2410_IRQ(20) +#define IRQ_SDI S3C2410_IRQ(21) +#define IRQ_SPI0 S3C2410_IRQ(22) +#define IRQ_UART1 S3C2410_IRQ(23) +#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ +#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ +#define IRQ_USBD S3C2410_IRQ(25) +#define IRQ_USBH S3C2410_IRQ(26) +#define IRQ_IIC S3C2410_IRQ(27) +#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ +#define IRQ_SPI1 S3C2410_IRQ(29) +#define IRQ_RTC S3C2410_IRQ(30) +#define IRQ_ADCPARENT S3C2410_IRQ(31) + +/* interrupts generated from the external interrupts sources */ +#define IRQ_EINT0_2412 S3C2410_IRQ(32) +#define IRQ_EINT1_2412 S3C2410_IRQ(33) +#define IRQ_EINT2_2412 S3C2410_IRQ(34) +#define IRQ_EINT3_2412 S3C2410_IRQ(35) +#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ +#define IRQ_EINT5 S3C2410_IRQ(37) +#define IRQ_EINT6 S3C2410_IRQ(38) +#define IRQ_EINT7 S3C2410_IRQ(39) +#define IRQ_EINT8 S3C2410_IRQ(40) +#define IRQ_EINT9 S3C2410_IRQ(41) +#define IRQ_EINT10 S3C2410_IRQ(42) +#define IRQ_EINT11 S3C2410_IRQ(43) +#define IRQ_EINT12 S3C2410_IRQ(44) +#define IRQ_EINT13 S3C2410_IRQ(45) +#define IRQ_EINT14 S3C2410_IRQ(46) +#define IRQ_EINT15 S3C2410_IRQ(47) +#define IRQ_EINT16 S3C2410_IRQ(48) +#define IRQ_EINT17 S3C2410_IRQ(49) +#define IRQ_EINT18 S3C2410_IRQ(50) +#define IRQ_EINT19 S3C2410_IRQ(51) +#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ +#define IRQ_EINT21 S3C2410_IRQ(53) +#define IRQ_EINT22 S3C2410_IRQ(54) +#define IRQ_EINT23 S3C2410_IRQ(55) + +#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) +#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) + +#define IRQ_LCD_FIFO S3C2410_IRQ(56) +#define IRQ_LCD_FRAME S3C2410_IRQ(57) + +/* IRQs for the interal UARTs, and ADC + * these need to be ordered in number of appearance in the + * SUBSRC mask register +*/ + +#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) + +#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ +#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) +#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) + +#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ +#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) +#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) + +#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ +#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) +#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) + +#define IRQ_TC S3C2410_IRQSUB(9) +#define IRQ_ADC S3C2410_IRQSUB(10) + +#define NR_IRQS_S3C2410 (S3C2410_IRQSUB(10) + 1) + +/* extra irqs for s3c2412 */ + +#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) + +#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) +#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) + +#define NR_IRQS_S3C2412 (S3C2410_IRQSUB(14) + 1) + +#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) +#define IRQ_S3C2416_DMA S3C2410_IRQ(17) +#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) +#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) +#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) + +#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) +#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) +#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) +#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) +#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) +#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) +#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) +#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) +#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) +#define IRQ_S32416_WDT S3C2410_IRQSUB(27) +#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) + +/* second interrupt-register of s3c2416/s3c2450 */ + +#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) +#define IRQ_S3C2416_2D S3C2416_IRQ(0) +#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) +#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) +#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3) +#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4) +#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5) +#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6) +#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7) + +#define NR_IRQS_S3C2416 (S3C2416_IRQ(7) + 1) + +/* extra irqs for s3c2440/s3c2442 */ + +#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ +#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ + +#define NR_IRQS_S3C2442 (S3C2410_IRQSUB(12) + 1) + +#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) +#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) + +#define NR_IRQS_S3C2440 (S3C2410_IRQSUB(14) + 1) + +/* irqs for s3c2443 */ + +#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ +#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ +#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ +#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ +#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ + +#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ + +#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 +#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC + +#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) +#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) +#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) +#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) + +#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) +#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) +#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) +#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) +#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) +#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) + +/* UART3 */ +#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) +#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) +#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) + +#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) +#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) + +#define NR_IRQS_S3C2443 (S3C2410_IRQSUB(28) + 1) + +/* compatibility define. */ +#define IRQ_UART3 IRQ_S3C2443_UART3 +#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 +#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 +#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 + +#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 +#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 + +#ifdef CONFIG_CPU_S3C2440 +#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 +#else +#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 +#endif + +/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ +#define FIQ_START IRQ_EINT0 + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c/irqs-s3c64xx.h b/arch/arm/mach-s3c/irqs-s3c64xx.h new file mode 100644 index 000000000000..c244e480e6b3 --- /dev/null +++ b/arch/arm/mach-s3c/irqs-s3c64xx.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - IRQ support + */ + +#ifndef __ASM_MACH_S3C64XX_IRQS_H +#define __ASM_MACH_S3C64XX_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S3C_IRQ_OFFSET (32) + +#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) + +#define IRQ_VIC0_BASE S3C_IRQ(0) +#define IRQ_VIC1_BASE S3C_IRQ(32) + +/* VIC based IRQs */ + +#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) +#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) + +/* VIC0 */ + +#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) +#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) +#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) +#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) +#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) +#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) +#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) +#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) +#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) +#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) +#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) +#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) +#define IRQ_2D S3C64XX_IRQ_VIC0(11) +#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) +#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) +#define IRQ_BATF S3C64XX_IRQ_VIC0(14) +#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) +#define IRQ_MFC S3C64XX_IRQ_VIC0(16) +#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) +#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) +#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) +#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) +#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) +#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) +#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) +#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) +#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) +#define IRQ_WDT S3C64XX_IRQ_VIC0(26) +#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) +#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) +#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) +#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) +#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) + +/* VIC1 */ + +#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) +#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) +#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) +#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) +#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) +#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) +#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) +#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) +#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) +#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) +#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) +#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) +#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) +#define IRQ_NFC S3C64XX_IRQ_VIC1(13) +#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) +#define IRQ_USBH S3C64XX_IRQ_VIC1(15) +#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) +#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) +#define IRQ_IIC S3C64XX_IRQ_VIC1(18) +#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) +#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) +#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) +#define IRQ_MSM S3C64XX_IRQ_VIC1(22) +#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) +#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) +#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) +#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ +#define IRQ_OTG S3C64XX_IRQ_VIC1(26) +#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) +#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) +#define IRQ_SEC S3C64XX_IRQ_VIC1(29) +#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) +#define IRQ_TC IRQ_PENDN +#define IRQ_ADC S3C64XX_IRQ_VIC1(31) + +/* compatibility for device defines */ + +#define IRQ_IIC1 IRQ_S3C6410_IIC1 + +/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series + * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE + * which we place after the pair of VICs. */ + +#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) + +#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) +#define IRQ_EINT(x) S3C_EINT(x) +#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) + +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP3_NR (5) +#define IRQ_EINT_GROUP4_NR (14) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +#define IRQ_EINT_GROUP7_NR (16) +#define IRQ_EINT_GROUP8_NR (15) +#define IRQ_EINT_GROUP9_NR (9) + +#define IRQ_EINT_GROUP_BASE S3C_EINT(28) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) + +/* Some boards have their own IRQs behind this */ +#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) + +/* Set the default nr_irqs, boards can override if necessary */ +#define S3C64XX_NR_IRQS IRQ_BOARD_START + +/* Compatibility */ + +#define IRQ_ONENAND IRQ_ONENAND0 +#define IRQ_I2S0 IRQ_S3C6410_IIS + +#endif /* __ASM_MACH_S3C64XX_IRQS_H */ + diff --git a/arch/arm/mach-s3c/irqs.h b/arch/arm/mach-s3c/irqs.h new file mode 100644 index 000000000000..0bff1c1c8eb0 --- /dev/null +++ b/arch/arm/mach-s3c/irqs.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "irqs-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "irqs-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c/mach-amlm5900.c b/arch/arm/mach-s3c/mach-amlm5900.c index 94c4512ace17..f85e5885e9b4 100644 --- a/arch/arm/mach-s3c/mach-amlm5900.c +++ b/arch/arm/mach-s3c/mach-amlm5900.c @@ -239,7 +239,9 @@ static void __init amlm5900_init(void) MACHINE_START(AML_M5900, "AML_M5900") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = amlm5900_map_io, + .nr_irqs = NR_IRQS_S3C2410, .init_irq = s3c2410_init_irq, .init_machine = amlm5900_init, .init_time = amlm5900_init_time, diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 60df40052209..4536f3e66e27 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -414,6 +414,7 @@ static void __init anubis_init(void) MACHINE_START(ANUBIS, "Simtec-Anubis") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2440, .map_io = anubis_map_io, .init_machine = anubis_init, .init_irq = s3c2440_init_irq, diff --git a/arch/arm/mach-s3c/mach-anw6410.c b/arch/arm/mach-s3c/mach-anw6410.c index 825714e9ac66..b67eae43e04f 100644 --- a/arch/arm/mach-s3c/mach-anw6410.c +++ b/arch/arm/mach-s3c/mach-anw6410.c @@ -40,7 +40,7 @@ #include "devs.h" #include "cpu.h" -#include +#include "irqs.h" #include "regs-gpio.h" #include "gpio-samsung.h" diff --git a/arch/arm/mach-s3c/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c index c6a5a51d84aa..743403d873e0 100644 --- a/arch/arm/mach-s3c/mach-at2440evb.c +++ b/arch/arm/mach-s3c/mach-at2440evb.c @@ -225,6 +225,7 @@ static void __init at2440evb_init(void) MACHINE_START(AT2440EVB, "AT2440EVB") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2440, .map_io = at2440evb_map_io, .init_machine = at2440evb_init, .init_irq = s3c2440_init_irq, diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index 5ac24e406157..a33ceab81e09 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -575,6 +575,7 @@ static void __init bast_init(void) MACHINE_START(BAST, "Simtec-BAST") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = bast_map_io, .init_irq = s3c2410_init_irq, .init_machine = bast_init, diff --git a/arch/arm/mach-s3c/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c index 5d1d4b67a4b7..4edde13b89b5 100644 --- a/arch/arm/mach-s3c/mach-crag6410-module.c +++ b/arch/arm/mach-s3c/mach-crag6410-module.c @@ -28,7 +28,7 @@ #include #include "cpu.h" -#include +#include "irqs.h" #include "crag6410.h" diff --git a/arch/arm/mach-s3c/mach-crag6410.c b/arch/arm/mach-s3c/mach-crag6410.c index e3e0fe897bcc..9a45474d1bf7 100644 --- a/arch/arm/mach-s3c/mach-crag6410.c +++ b/arch/arm/mach-s3c/mach-crag6410.c @@ -47,7 +47,7 @@ #include "map.h" #include "regs-gpio.h" #include "gpio-samsung.h" -#include +#include "irqs.h" #include "fb.h" #include "sdhci.h" diff --git a/arch/arm/mach-s3c/mach-gta02.c b/arch/arm/mach-s3c/mach-gta02.c index 418939ce0fc3..abfdce765525 100644 --- a/arch/arm/mach-s3c/mach-gta02.c +++ b/arch/arm/mach-s3c/mach-gta02.c @@ -572,6 +572,7 @@ static void __init gta02_init_time(void) MACHINE_START(NEO1973_GTA02, "GTA02") /* Maintainer: Nelson Castillo */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2442, .map_io = gta02_map_io, .init_irq = s3c2442_init_irq, .init_machine = gta02_machine_init, diff --git a/arch/arm/mach-s3c/mach-h1940.c b/arch/arm/mach-s3c/mach-h1940.c index 8a43ed1c4c4d..032b18837855 100644 --- a/arch/arm/mach-s3c/mach-h1940.c +++ b/arch/arm/mach-s3c/mach-h1940.c @@ -793,6 +793,7 @@ static void __init h1940_init(void) MACHINE_START(H1940, "IPAQ-H1940") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = h1940_map_io, .reserve = h1940_reserve, .init_irq = s3c2410_init_irq, diff --git a/arch/arm/mach-s3c/mach-hmt.c b/arch/arm/mach-s3c/mach-hmt.c index b287e9987311..49ba16c447aa 100644 --- a/arch/arm/mach-s3c/mach-hmt.c +++ b/arch/arm/mach-s3c/mach-hmt.c @@ -26,7 +26,7 @@ #include