From 8060646a0fd1b1685a16694f2eb2f461e5eb46cc Mon Sep 17 00:00:00 2001 From: Jiri Pirko Date: Thu, 3 Dec 2015 12:12:23 +0100 Subject: mlxsw: core: Add support for packets received from LAG port Lower layer (pci) has information if the packet is received via LAG port. If that is the case, it fills up rx_info accordingly. However upper layer does not care about lag_id/port_index for received packets so convert it to local_port before passing it up. For that conversion, lag mapping array is introduced. Upper layer is responsible for setting up the mapping according to what is set in HW. Signed-off-by: Jiri Pirko Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/net/ethernet/mellanox/mlxsw/pci.c') diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index de69e719dc9d..8ca66a01b097 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -690,7 +690,9 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, if (mlxsw_pci_cqe_lag_get(cqe)) goto drop; - rx_info.sys_port = mlxsw_pci_cqe_system_port_get(cqe); + rx_info.is_lag = false; + rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); + rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); byte_count = mlxsw_pci_cqe_byte_count_get(cqe); -- cgit