/* * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org), * derived from r4xx0.c by David S. Miller (davem@davemloft.net). */ #include #include #include #include #include #include #include #include #include #include #include #include /* Secondary cache size in bytes, if present. */ static unsigned long scache_size; #define SC_LINE 32 #define SC_PAGE (128*SC_LINE) static inline void blast_r5000_scache(void) { unsigned long start = INDEX_BASE; unsigned long end = start + scache_size; while(start < end) { cache_op(R5K_Page_Invalidate_S, start); start += SC_PAGE; } } static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size) { unsigned long end, a; /* Catch bad driver code */ BUG_ON(size == 0); if (size >= scache_size) { blast_r5000_scache(); return; } /* On the R5000 secondary cache we cannot * invalidate less than a page at a time. * The secondary cache is physically indexed, write-through. */ a = addr & ~(SC_PAGE - 1); end = (addr + size - 1) & ~(SC_PAGE - 1); while (a <= end) { cache_op(R5K_Page_Invalidate_S, a); a += SC_PAGE; } } static void r5k_sc_enable(void) { unsigned long flags; local_irq_save(flags); set_c0_config(R5K_CONF_SE); blast_r5000_scache(); local_irq_restore(flags); } static void r5k_sc_disable(void) { unsigned long flags; local_irq_save(flags); blast_r5000_scache(); clear_c0_config(R5K_CONF_SE); local_irq_restore(flags); } static inline int __init r5k_sc_probe(void) { unsigned long config = read_c0_config(); if (config & CONF_SC) return(0); scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20); printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n", scache_size >> 10); return 1; } static struct bcache_ops r5k_sc_ops = { .bc_enable = r5k_sc_enable, .bc_disable = r5k_sc_disable, .bc_wback_inv = r5k_dma_cache_inv_sc, .bc_inv = r5k_dma_cache_inv_sc }; void __cpuinit r5k_sc_init(void) { if (r5k_sc_probe()) { r5k_sc_enable(); bcops = &r5k_sc_ops; } } -pytest-docs'>CHECK/initial-pytest-docs mirror/u-boot.git
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path: root/include/configs/W7OLMG.h
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/*
 * (C) Copyright 2001
 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
#define CONFIG_4xx		1		/* ...member of PPC405 family	*/
#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
#define CONFIG_W7OLMG		1		/* ...specifically an LMG	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
#define	CONFIG_MISC_INIT_R	1		/* and misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/

#if 1
#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
#else
#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
#endif

#undef CONFIG_BOOTARGS

#define CONFIG_LOADADDR		F0080000

#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_IPADDR		192.168.1.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_SERVERIP		192.168.1.2

#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
#undef CONFIG_SYS_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1		/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0		/* PHY address			*/

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
#define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS  {2, 4}           /* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_DTT


#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/

#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
#undef  CONFIG_SYS_HUSH_PARSER				/* No hush parse for U-Boot       */
#ifdef  CONFIG_SYS_HUSH_PARSER
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef  CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
#define CONFIG_SYS_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD		384000


/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{9600}

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
#define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */

#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */