// SPDX-License-Identifier: GPL-2.0 /* * lib/locking-selftest.c * * Testsuite for various locking APIs: spinlocks, rwlocks, * mutexes and rw-semaphores. * * It is checking both false positives and false negatives. * * Started by Ingo Molnar: * * Copyright (C) 2006 Red Hat, Inc., Ingo Molnar */ #include #include #include #include #include #include #include #include #include #include #include #include /* * Change this to 1 if you want to see the failure printouts: */ static unsigned int debug_locks_verbose; static DEFINE_WW_CLASS(ww_lockdep); static int __init setup_debug_locks_verbose(char *str) { get_option(&str, &debug_locks_verbose); return 1; } __setup("debug_locks_verbose=", setup_debug_locks_verbose); #define FAILURE 0 #define SUCCESS 1 #define LOCKTYPE_SPIN 0x1 #define LOCKTYPE_RWLOCK 0x2 #define LOCKTYPE_MUTEX 0x4 #define LOCKTYPE_RWSEM 0x8 #define LOCKTYPE_WW 0x10 #define LOCKTYPE_RTMUTEX 0x20 static struct ww_acquire_ctx t, t2; static struct ww_mutex o, o2, o3; /* * Normal standalone locks, for the circular and irq-context * dependency tests: */ static DEFINE_RAW_SPINLOCK(lock_A); static DEFINE_RAW_SPINLOCK(lock_B); static DEFINE_RAW_SPINLOCK(lock_C); static DEFINE_RAW_SPINLOCK(lock_D); static DEFINE_RWLOCK(rwlock_A); static DEFINE_RWLOCK(rwlock_B); static DEFINE_RWLOCK(rwlock_C); static DEFINE_RWLOCK(rwlock_D); static DEFINE_MUTEX(mutex_A); static DEFINE_MUTEX(mutex_B); static DEFINE_MUTEX(mutex_C); static DEFINE_MUTEX(mutex_D); static DECLARE_RWSEM(rwsem_A); static DECLARE_RWSEM(rwsem_B); static DECLARE_RWSEM(rwsem_C); static DECLARE_RWSEM(rwsem_D); #ifdef CONFIG_RT_MUTEXES static DEFINE_RT_MUTEX(rtmutex_A); static DEFINE_RT_MUTEX(rtmutex_B); static DEFINE_RT_MUTEX(rtmutex_C); static DEFINE_RT_MUTEX(rtmutex_D); #endif /* * Locks that we initialize dynamically as well so that * e.g. X1 and X2 becomes two instances of the same class, * but X* and Y* are different classes. We do this so that * we do not trigger a real lockup: */ static DEFINE_RAW_SPINLOCK(lock_X1); static DEFINE_RAW_SPINLOCK(lock_X2); static DEFINE_RAW_SPINLOCK(lock_Y1); static DEFINE_RAW_SPINLOCK(lock_Y2); static DEFINE_RAW_SPINLOCK(lock_Z1); static DEFINE_RAW_SPINLOCK(lock_Z2); static DEFINE_RWLOCK(rwlock_X1); static DEFINE_RWLOCK(rwlock_X2); static DEFINE_RWLOCK(rwlock_Y1); static DEFINE_RWLOCK(rwlock_Y2); static DEFINE_RWLOCK(rwlock_Z1); static DEFINE_RWLOCK(rwlock_Z2); static DEFINE_MUTEX(mutex_X1); static DEFINE_MUTEX(mutex_X2); static DEFINE_MUTEX(mutex_Y1); static DEFINE_MUTEX(mutex_Y2); static DEFINE_MUTEX(mutex_Z1); static DEFINE_MUTEX(mutex_Z2); static DECLARE_RWSEM(rwsem_X1); static DECLARE_RWSEM(rwsem_X2); static DECLARE_RWSEM(rwsem_Y1); static DECLARE_RWSEM(rwsem_Y2); static DECLARE_RWSEM(rwsem_Z1); static DECLARE_RWSEM(rwsem_Z2); #ifdef CONFIG_RT_MUTEXES static DEFINE_RT_MUTEX(rtmutex_X1); static DEFINE_RT_MUTEX(rtmutex_X2); static DEFINE_RT_MUTEX(rtmutex_Y1); static DEFINE_RT_MUTEX(rtmutex_Y2); static DEFINE_RT_MUTEX(rtmutex_Z1); static DEFINE_RT_MUTEX(rtmutex_Z2); #endif /* * non-inlined runtime initializers, to let separate locks share * the same lock-class: */ #define INIT_CLASS_FUNC(class) \ static noinline void \ init_class_##class(raw_spinlock_t *lock, rwlock_t *rwlock, \ struct mutex *mutex, struct rw_semaphore *rwsem)\ { \ raw_spin_lock_init(lock); \ rwlock_init(rwlock); \ mutex_init(mutex); \ init_rwsem(rwsem); \ } INIT_CLASS_FUNC(X) INIT_CLASS_FUNC(Y) INIT_CLASS_FUNC(Z) static void init_shared_classes(void) { #ifdef CONFIG_RT_MUTEXES static struct lock_class_key rt_X, rt_Y, rt_Z; __rt_mutex_init(&rtmutex_X1, __func__, &rt_X); __rt_mutex_init(&rtmutex_X2, __func__, &rt_X); __rt_mutex_init(&rtmutex_Y1, __func__, &rt_Y); __rt_mutex_init(&rtmutex_Y2, __func__, &rt_Y); __rt_mutex_init(&rtmutex_Z1, __func__, &rt_Z); __rt_mutex_init(&rtmutex_Z2, __func__, &rt_Z); #endif init_class_X(&lock_X1, &rwlock_X1, &mutex_X1, &rwsem_X1); init_class_X(&lock_X2, &rwlock_X2, &mutex_X2, &rwsem_X2); init_class_Y(&lock_Y1, &rwlock_Y1, &mutex_Y1, &rwsem_Y1); init_class_Y(&lock_Y2, &rwlock_Y2, &mutex_Y2, &rwsem_Y2); init_class_Z(&lock_Z1, &rwlock_Z1, &mutex_Z1, &rwsem_Z1); init_class_Z(&lock_Z2, &rwlock_Z2, &mutex_Z2, &rwsem_Z2); } /* * For spinlocks and rwlocks we also do hardirq-safe / softirq-safe tests. * The following functions use a lock from a simulated hardirq/softirq * context, causing the locks to be marked as hardirq-safe/softirq-safe: */ #define HARDIRQ_DISABLE local_irq_disable #define HARDIRQ_ENABLE local_irq_enable #define HARDIRQ_ENTER() \ local_irq_disable(); \ __irq_enter(); \ WARN_ON(!in_irq()); #define HARDIRQ_EXIT() \ __irq_exit(); \ local_irq_enable(); #define SOFTIRQ_DISABLE local_bh_disable #define SOFTIRQ_ENABLE local_bh_enable #define SOFTIRQ_ENTER() \ local_bh_disable(); \ local_irq_disable(); \ lockdep_softirq_enter(); \ WARN_ON(!in_softirq()); #define SOFTIRQ_EXIT() \ lockdep_softirq_exit(); \ local_irq_enable(); \ local_bh_enable(); /* * Shortcuts for lock/unlock API variants, to keep * the testcases compact: */ #define L(x) raw_spin_lock(&lock_##x) #define U(x) raw_spin_unlock(&lock_##x) #define LU(x) L(x); U(x) #define SI(x) raw_spin_lock_init(&lock_##x) #define WL(x) write_lock(&rwlock_##x) #define WU(x) write_unlock(&rwlock_##x) #define WLU(x) WL(x); WU(x) #define RL(x) read_lock(&rwlock_##x) #define RU(x) read_unlock(&rwlock_##x) #define RLU(x) RL(x); RU(x) #define RWI(x) rwlock_init(&rwlock_##x) #define ML(x) mutex_lock(&mutex_##x) #define MU(x) mutex_unlock(&mutex_##x) #define MI(x) mutex_init(&mutex_##x) #define RTL(x) rt_mutex_lock(&rtmutex_##x) #define RTU(x) rt_mutex_unlock(&rtmutex_##x) #define RTI(x) rt_mutex_init(&rtmutex_##x) #define WSL(x) down_write(&rwsem_##x) #define WSU(x) up_write(&rwsem_##x) #define RSL(x) down_read(&rwsem_##x) #define RSU(x) up_read(&rwsem_##x) #define RWSI(x) init_rwsem(&rwsem_##x) #ifndef CONFIG_DEBUG_WW_MUTEX_SLOWPATH #define WWAI(x) ww_acquire_init(x, &ww_lockdep) #else #define WWAI(x) do { ww_acquire_init(x, &ww_lockdep); (x)->deadlock_inject_countdown = ~0U; } while (0) #endif #define WWAD(x) ww_acquire_done(x) #define WWAF(x) ww_acquire_fini(x) #define WWL(x, c) ww_mutex_lock(x, c) #define WWT(x) ww_mutex_trylock(x) #define WWL1(x) ww_mutex_lock(x, NULL) #define WWU(x) ww_mutex_unlock(x) #define LOCK_UNLOCK_2(x,y) LOCK(x); LOCK(y); UNLOCK(y); UNLOCK(x) /* * Generate different permutations of the same testcase, using * the same basic lock-dependency/state events: */ #define GENERATE_TESTCASE(name) \ \ static void name(void) { E(); } #define GENERATE_PERMUTATIONS_2_EVENTS(name) \ \ static void name##_12(void) { E1(); E2(); } \ static void name##_21(void) { E2(); E1(); } #define GENERATE_PERMUTATIONS_3_EVENTS(name) \ \ static void name##_123(void) { E1(); E2(); E3(); } \ static void name##_132(void) { E1(); E3(); E2(); } \ static void name##_213(void) { E2(); E1(); E3(); } \ static void name##_231(void) { E2(); E3(); E1(); } \ static void name##_312(void) { E3(); E1(); E2(); } \ static void name##_321(void) { E3(); E2(); E1(); } /* * AA deadlock: */ #define E() \ \ LOCK(X1); \ LOCK(X2); /* this one should fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(AA_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(AA_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(AA_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(AA_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(AA_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(AA_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(AA_rtmutex); #endif #undef E /* * Special-case for read-locking, they are * allowed to recurse on the same lock class: */ static void rlock_AA1(void) { RL(X1); RL(X1); // this one should NOT fail } static void rlock_AA1B(void) { RL(X1); RL(X2); // this one should NOT fail } static void rsem_AA1(void) { RSL(X1); RSL(X1); // this one should fail } static void rsem_AA1B(void) { RSL(X1); RSL(X2); // this one should fail } /* * The mixing of read and write locks is not allowed: */ static void rlock_AA2(void) { RL(X1); WL(X2); // this one should fail } static void rsem_AA2(void) { RSL(X1); WSL(X2); // this one should fail } static void rlock_AA3(void) { WL(X1); RL(X2); // this one should fail } static void rsem_AA3(void) { WSL(X1); RSL(X2); // this one should fail } /* * read_lock(A) * spin_lock(B) * spin_lock(B) * write_lock(A) */ static void rlock_ABBA1(void) { RL(X1); L(Y1); U(Y1); RU(X1); L(Y1); WL(X1); WU(X1); U(Y1); // should fail } static void rwsem_ABBA1(void) { RSL(X1); ML(Y1); MU(Y1); RSU(X1); ML(Y1); WSL(X1); WSU(X1); MU(Y1); // should fail } /* * read_lock(A) * spin_lock(B) * spin_lock(B) * read_lock(A) */ static void rlock_ABBA2(void) { RL(X1); L(Y1); U(Y1); RU(X1); L(Y1); RL(X1); RU(X1); U(Y1); // should NOT fail } static void rwsem_ABBA2(void) { RSL(X1); ML(Y1); MU(Y1); RSU(X1); ML(Y1); RSL(X1); RSU(X1); MU(Y1); // should fail } /* * write_lock(A) * spin_lock(B) * spin_lock(B) * write_lock(A) */ static void rlock_ABBA3(void) { WL(X1); L(Y1); U(Y1); WU(X1); L(Y1); WL(X1); WU(X1); U(Y1); // should fail } static void rwsem_ABBA3(void) { WSL(X1); ML(Y1); MU(Y1); WSU(X1); ML(Y1); WSL(X1); WSU(X1); MU(Y1); // should fail } /* * ABBA deadlock: */ #define E() \ \ LOCK_UNLOCK_2(A, B); \ LOCK_UNLOCK_2(B, A); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(ABBA_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(ABBA_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(ABBA_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(ABBA_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(ABBA_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(ABBA_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(ABBA_rtmutex); #endif #undef E /* * AB BC CA deadlock: */ #define E() \ \ LOCK_UNLOCK_2(A, B); \ LOCK_UNLOCK_2(B, C); \ LOCK_UNLOCK_2(C, A); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(ABBCCA_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(ABBCCA_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(ABBCCA_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(ABBCCA_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(ABBCCA_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(ABBCCA_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(ABBCCA_rtmutex); #endif #undef E /* * AB CA BC deadlock: */ #define E() \ \ LOCK_UNLOCK_2(A, B); \ LOCK_UNLOCK_2(C, A); \ LOCK_UNLOCK_2(B, C); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(ABCABC_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(ABCABC_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(ABCABC_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(ABCABC_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(ABCABC_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(ABCABC_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(ABCABC_rtmutex); #endif #undef E /* * AB BC CD DA deadlock: */ #define E() \ \ LOCK_UNLOCK_2(A, B); \ LOCK_UNLOCK_2(B, C); \ LOCK_UNLOCK_2(C, D); \ LOCK_UNLOCK_2(D, A); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(ABBCCDDA_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(ABBCCDDA_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(ABBCCDDA_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(ABBCCDDA_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(ABBCCDDA_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(ABBCCDDA_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(ABBCCDDA_rtmutex); #endif #undef E /* * AB CD BD DA deadlock: */ #define E() \ \ LOCK_UNLOCK_2(A, B); \ LOCK_UNLOCK_2(C, D); \ LOCK_UNLOCK_2(B, D); \ LOCK_UNLOCK_2(D, A); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(ABCDBDDA_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(ABCDBDDA_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(ABCDBDDA_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(ABCDBDDA_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(ABCDBDDA_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(ABCDBDDA_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(ABCDBDDA_rtmutex); #endif #undef E /* * AB CD BC DA deadlock: */ #define E() \ \ LOCK_UNLOCK_2(A, B); \ LOCK_UNLOCK_2(C, D); \ LOCK_UNLOCK_2(B, C); \ LOCK_UNLOCK_2(D, A); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(ABCDBCDA_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(ABCDBCDA_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(ABCDBCDA_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(ABCDBCDA_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(ABCDBCDA_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(ABCDBCDA_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(ABCDBCDA_rtmutex); #endif #undef E /* * Double unlock: */ #define E() \ \ LOCK(A); \ UNLOCK(A); \ UNLOCK(A); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(double_unlock_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(double_unlock_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(double_unlock_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(double_unlock_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(double_unlock_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(double_unlock_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(double_unlock_rtmutex); #endif #undef E /* * initializing a held lock: */ #define E() \ \ LOCK(A); \ INIT(A); /* fail */ /* * 6 testcases: */ #include "locking-selftest-spin.h" GENERATE_TESTCASE(init_held_spin) #include "locking-selftest-wlock.h" GENERATE_TESTCASE(init_held_wlock) #include "locking-selftest-rlock.h" GENERATE_TESTCASE(init_held_rlock) #include "locking-selftest-mutex.h" GENERATE_TESTCASE(init_held_mutex) #include "locking-selftest-wsem.h" GENERATE_TESTCASE(init_held_wsem) #include "locking-selftest-rsem.h" GENERATE_TESTCASE(init_held_rsem) #ifdef CONFIG_RT_MUTEXES #include "locking-selftest-rtmutex.h" GENERATE_TESTCASE(init_held_rtmutex); #endif #undef E /* * locking an irq-safe lock with irqs enabled: */ #define E1() \ \ IRQ_ENTER(); \ LOCK(A); \ UNLOCK(A); \ IRQ_EXIT(); #define E2() \ \ LOCK(A); \ UNLOCK(A); /* * Generate 24 testcases: */ #include "locking-selftest-spin-hardirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe1_hard_spin) #include "locking-selftest-rlock-hardirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe1_hard_rlock) #include "locking-selftest-wlock-hardirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe1_hard_wlock) #include "locking-selftest-spin-softirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe1_soft_spin) #include "locking-selftest-rlock-softirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe1_soft_rlock) #include "locking-selftest-wlock-softirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe1_soft_wlock) #undef E1 #undef E2 /* * Enabling hardirqs with a softirq-safe lock held: */ #define E1() \ \ SOFTIRQ_ENTER(); \ LOCK(A); \ UNLOCK(A); \ SOFTIRQ_EXIT(); #define E2() \ \ HARDIRQ_DISABLE(); \ LOCK(A); \ HARDIRQ_ENABLE(); \ UNLOCK(A); /* * Generate 12 testcases: */ #include "locking-selftest-spin.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2A_spin) #include "locking-selftest-wlock.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2A_wlock) #include "locking-selftest-rlock.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2A_rlock) #undef E1 #undef E2 /* * Enabling irqs with an irq-safe lock held: */ #define E1() \ \ IRQ_ENTER(); \ LOCK(A); \ UNLOCK(A); \ IRQ_EXIT(); #define E2() \ \ IRQ_DISABLE(); \ LOCK(A); \ IRQ_ENABLE(); \ UNLOCK(A); /* * Generate 24 testcases: */ #include "locking-selftest-spin-hardirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2B_hard_spin) #include "locking-selftest-rlock-hardirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2B_hard_rlock) #include "locking-selftest-wlock-hardirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2B_hard_wlock) #include "locking-selftest-spin-softirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2B_soft_spin) #include "locking-selftest-rlock-softirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2B_soft_rlock) #include "locking-selftest-wlock-softirq.h" GENERATE_PERMUTATIONS_2_EVENTS(irqsafe2B_soft_wlock) #undef E1 #undef E2 /* * Acquiring a irq-unsafe lock while holding an irq-safe-lock: */ #define E1() \ \ LOCK(A); \ LOCK(B); \ UNLOCK(B); \ UNLOCK(A); \ #define E2() \ \ LOCK(B); \ UNLOCK(B); #define E3() \ \ IRQ_ENTER(); \ LOCK(A); \ UNLOCK(A); \ IRQ_EXIT(); /* * Generate 36 testcases: */ #include "locking-selftest-spin-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe3_hard_spin) #include "locking-selftest-rlock-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe3_hard_rlock) #include "locking-selftest-wlock-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe3_hard_wlock) #include "locking-selftest-spin-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe3_soft_spin) #include "locking-selftest-rlock-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe3_soft_rlock) #include "locking-selftest-wlock-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe3_soft_wlock) #undef E1 #undef E2 #undef E3 /* * If a lock turns into softirq-safe, but earlier it took * a softirq-unsafe lock: */ #define E1() \ IRQ_DISABLE(); \ LOCK(A); \ LOCK(B); \ UNLOCK(B); \ UNLOCK(A); \ IRQ_ENABLE(); #define E2() \ LOCK(B); \ UNLOCK(B); #define E3() \ IRQ_ENTER(); \ LOCK(A); \ UNLOCK(A); \ IRQ_EXIT(); /* * Generate 36 testcases: */ #include "locking-selftest-spin-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe4_hard_spin) #include "locking-selftest-rlock-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe4_hard_rlock) #include "locking-selftest-wlock-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe4_hard_wlock) #include "locking-selftest-spin-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe4_soft_spin) #include "locking-selftest-rlock-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe4_soft_rlock) #include "locking-selftest-wlock-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irqsafe4_soft_wlock) #undef E1 #undef E2 #undef E3 /* * read-lock / write-lock irq inversion. * * Deadlock scenario: * * CPU#1 is at #1, i.e. it has write-locked A, but has not * taken B yet. * * CPU#2 is at #2, i.e. it has locked B. * * Hardirq hits CPU#2 at point #2 and is trying to read-lock A. * * The deadlock occurs because CPU#1 will spin on B, and CPU#2 * will spin on A. */ #define E1() \ \ IRQ_DISABLE(); \ WL(A); \ LOCK(B); \ UNLOCK(B); \ WU(A); \ IRQ_ENABLE(); #define E2() \ \ LOCK(B); \ UNLOCK(B); #define E3() \ \ IRQ_ENTER(); \ RL(A); \ RU(A); \ IRQ_EXIT(); /* * Generate 36 testcases: */ #include "locking-selftest-spin-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_inversion_hard_spin) #include "locking-selftest-rlock-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_inversion_hard_rlock) #include "locking-selftest-wlock-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_inversion_hard_wlock) #include "locking-selftest-spin-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_inversion_soft_spin) #include "locking-selftest-rlock-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_inversion_soft_rlock) #include "locking-selftest-wlock-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_inversion_soft_wlock) #undef E1 #undef E2 #undef E3 /* * read-lock / write-lock recursion that is actually safe. */ #define E1() \ \ IRQ_DISABLE(); \ WL(A); \ WU(A); \ IRQ_ENABLE(); #define E2() \ \ RL(A); \ RU(A); \ #define E3() \ \ IRQ_ENTER(); \ RL(A); \ L(B); \ U(B); \ RU(A); \ IRQ_EXIT(); /* * Generate 12 testcases: */ #include "locking-selftest-hardirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_read_recursion_hard) #include "locking-selftest-softirq.h" GENERATE_PERMUTATIONS_3_EVENTS(irq_read_recursion_soft) #undef E1 #undef E2 #undef E3 /* * read-lock / write-lock recursion that is unsafe. */ #define E1() \ \ IRQ_DISABLE(); \ L(B); \ WL(A); \ WU(A); \ U(B); \ IRQ_ENABLE(); #define E2() \ \ RL(A); \ RU(A); \ #define E3() \ \ IRQ_ENTER(); \ L(B); \ U(B); \ IRQ_EXIT(); /* * Generate 12 testcases: */ #include "locking-selftest-hardirq.h" // GENERATE_PERMUTATIONS_3_EVENTS(irq_read_recursion2_hard) #include "locking-selftest-softirq.h" // GENERATE_PERMUTATIONS_3_EVENTS(irq_read_recursion2_soft) #ifdef CONFIG_DEBUG_LOCK_ALLOC # define I_SPINLOCK(x) lockdep_reset_lock(&lock_##x.dep_map) # define I_RWLOCK(x) lockdep_reset_lock(&rwlock_##x.dep_map) # define I_MUTEX(x) lockdep_reset_lock(&mutex_##x.dep_map) # define I_RWSEM(x) lockdep_reset_lock(&rwsem_##x.dep_map) # define I_WW(x) lockdep_reset_lock(&x.dep_map) #ifdef CONFIG_RT_MUTEXES # define I_RTMUTEX(x) lockdep_reset_lock(&rtmutex_##x.dep_map) #endif #else # define I_SPINLOCK(x) # define I_RWLOCK(x) # define I_MUTEX(x) # define I_RWSEM(x) # define I_WW(x) #endif #ifndef I_RTMUTEX # define I_RTMUTEX(x) #endif #ifdef CONFIG_RT_MUTEXES #define I2_RTMUTEX(x) rt_mutex_init(&rtmutex_##x) #else #define I2_RTMUTEX(x) #endif #define I1(x) \ do { \ I_SPINLOCK(x); \ I_RWLOCK(x); \ I_MUTEX(x); \ I_RWSEM(x); \ I_RTMUTEX(x); \ } while (0) #define I2(x) \ do { \ raw_spin_lock_init(&lock_##x); \ rwlock_init(&rwlock_##x); \ mutex_init(&mutex_##x); \ init_rwsem(&rwsem_##x); \ I2_RTMUTEX(x); \ } while (0) static void reset_locks(void) { local_irq_disable(); lockdep_free_key_range(&ww_lockdep.acquire_key, 1); lockdep_free_key_range(&ww_lockdep.mutex_key, 1); I1(A); I1(B); I1(C); I1(D); I1(X1); I1(X2); I1(Y1); I1(Y2); I1(Z1); I1(Z2); I_WW(t); I_WW(t2); I_WW(o.base); I_WW(o2.base); I_WW(o3.base); lockdep_reset(); I2(A); I2(B); I2(C); I2(D); init_shared_classes(); ww_mutex_init(&o, &ww_lockdep); ww_mutex_init(&o2, &ww_lockdep); ww_mutex_init(&o3, &ww_lockdep); memset(&t, 0, sizeof(t)); memset(&t2, 0, sizeof(t2)); memset(&ww_lockdep.acquire_key, 0, sizeof(ww_lockdep.acquire_key)); memset(&ww_lockdep.mutex_key, 0, sizeof(ww_lockdep.mutex_key)); local_irq_enable(); } #undef I static int testcase_total; static int testcase_successes; static int expected_testcase_failures; static int unexpected_testcase_failures; static void dotest(void (*testcase_fn)(void), int expected, int lockclass_mask) { unsigned long saved_preempt_count = preempt_count(); WARN_ON(irqs_disabled()); testcase_fn(); /* * Filter out expected failures: */ #ifndef CONFIG_PROVE_LOCKING if (expected == FAILURE && debug_locks) { expected_testcase_failures++; pr_cont("failed|"); } else #endif if (debug_locks != expected) { unexpected_testcase_failures++; pr_cont("FAILED|"); } else { testcase_successes++; pr_cont(" ok |"); } testcase_total++; if (debug_locks_verbose) pr_cont(" lockclass mask: %x, debug_locks: %d, expected: %d\n", lockclass_mask, debug_locks, expected); /* * Some tests (e.g. double-unlock) might corrupt the preemption * count, so restore it: */ preempt_count_set(saved_preempt_count); #ifdef CONFIG_TRACE_IRQFLAGS if (softirq_count()) current->softirqs_enabled = 0; else current->softirqs_enabled = 1; #endif reset_locks(); } #ifdef CONFIG_RT_MUTEXES #define dotest_rt(fn, e, m) dotest((fn), (e), (m)) #else #define dotest_rt(fn, e, m) #endif static inline void print_testname(const char *testname) { printk("%33s:", testname); } #define DO_TESTCASE_1(desc, name, nr) \ print_testname(desc"/"#nr); \ dotest(name##_##nr, SUCCESS, LOCKTYPE_RWLOCK); \ pr_cont("\n"); #define DO_TESTCASE_1B(desc, name, nr) \ print_testname(desc"/"#nr); \ dotest(name##_##nr, FAILURE, LOCKTYPE_RWLOCK); \ pr_cont("\n"); #define DO_TESTCASE_3(desc, name, nr) \ print_testname(desc"/"#nr); \ dotest(name##_spin_##nr, FAILURE, LOCKTYPE_SPIN); \ dotest(name##_wlock_##nr, FAILURE, LOCKTYPE_RWLOCK); \ dotest(name##_rlock_##nr, SUCCESS, LOCKTYPE_RWLOCK); \ pr_cont("\n"); #define DO_TESTCASE_3RW(desc, name, nr) \ print_testname(desc"/"#nr); \ dotest(name##_spin_##nr, FAILURE, LOCKTYPE_SPIN|LOCKTYPE_RWLOCK);\ dotest(name##_wlock_##nr, FAILURE, LOCKTYPE_RWLOCK); \ dotest(name##_rlock_##nr, SUCCESS, LOCKTYPE_RWLOCK); \ pr_cont("\n"); #define DO_TESTCASE_6(desc, name) \ print_testname(desc); \ dotest(name##_spin, FAILURE, LOCKTYPE_SPIN); \ dotest(name##_wlock, FAILURE, LOCKTYPE_RWLOCK); \ dotest(name##_rlock, FAILURE, LOCKTYPE_RWLOCK); \ dotest(name##_mutex, FAILURE, LOCKTYPE_MUTEX); \ dotest(name##_wsem, FAILURE, LOCKTYPE_RWSEM); \ dotest(name##_rsem, FAILURE, LOCKTYPE_RWSEM); \ dotest_rt(name##_rtmutex, FAILURE, LOCKTYPE_RTMUTEX); \ pr_cont("\n"); #define DO_TESTCASE_6_SUCCESS(desc, name) \ print_testname(desc); \ dotest(name##_spin, SUCCESS, LOCKTYPE_SPIN); \ dotest(name##_wlock, SUCCESS, LOCKTYPE_RWLOCK); \ dotest(name##_rlock, SUCCESS, LOCKTYPE_RWLOCK); \ dotest(name##_mutex, SUCCESS, LOCKTYPE_MUTEX); \ dotest(name##_wsem, SUCCESS, LOCKTYPE_RWSEM); \ dotest(name##_rsem, SUCCESS, LOCKTYPE_RWSEM); \ dotest_rt(name##_rtmutex, SUCCESS, LOCKTYPE_RTMUTEX); \ pr_cont("\n"); /* * 'read' variant: rlocks must not trigger. */ #define DO_TESTCASE_6R(desc, name) \ print_testname(desc); \ dotest(name##_spin, FAILURE, LOCKTYPE_SPIN); \ dotest(name##_wlock, FAILURE, LOCKTYPE_RWLOCK); \ dotest(name##_rlock, SUCCESS, LOCKTYPE_RWLOCK); \ dotest(name##_mutex, FAILURE, LOCKTYPE_MUTEX); \ dotest(name##_wsem, FAILURE, LOCKTYPE_RWSEM); \ dotest(name##_rsem, FAILURE, LOCKTYPE_RWSEM); \ dotest_rt(name##_rtmutex, FAILURE, LOCKTYPE_RTMUTEX); \ pr_cont("\n"); #define DO_TESTCASE_2I(desc, name, nr) \ DO_TESTCASE_1("hard-"desc, name##_hard, nr); \ DO_TESTCASE_1("soft-"desc, name##_soft, nr); #define DO_TESTCASE_2IB(desc, name, nr) \ DO_TESTCASE_1B("hard-"desc, name##_hard, nr); \ DO_TESTCASE_1B("soft-"desc, name##_soft, nr); #define DO_TESTCASE_6I(desc, name, nr) \ DO_TESTCASE_3("hard-"desc, name##_hard, nr); \ DO_TESTCASE_3("soft-"desc, name##_soft, nr); #define DO_TESTCASE_6IRW(desc, name, nr) \ DO_TESTCASE_3RW("hard-"desc, name##_hard, nr); \ DO_TESTCASE_3RW("soft-"desc, name##_soft, nr); #define DO_TESTCASE_2x3(desc, name) \ DO_TESTCASE_3(desc, name, 12); \ DO_TESTCASE_3(desc, name, 21); #define DO_TESTCASE_2x6(desc, name) \ DO_TESTCASE_6I(desc, name, 12); \ DO_TESTCASE_6I(desc, name, 21); #define DO_TESTCASE_6x2(desc, name) \ DO_TESTCASE_2I(desc, name, 123); \ DO_TESTCASE_2I(desc, name, 132); \ DO_TESTCASE_2I(desc, name, 213); \ DO_TESTCASE_2I(desc, name, 231); \ DO_TESTCASE_2I(desc, name, 312); \ DO_TESTCASE_2I(desc, name, 321); #define DO_TESTCASE_6x2B(desc, name) \ DO_TESTCASE_2IB(desc, name, 123); \ DO_TESTCASE_2IB(desc, name, 132); \ DO_TESTCASE_2IB(desc, name, 213); \ DO_TESTCASE_2IB(desc, name, 231); \ DO_TESTCASE_2IB(desc, name, 312); \ DO_TESTCASE_2IB(desc, name, 321); #define DO_TESTCASE_6x6(desc, name) \ DO_TESTCASE_6I(desc, name, 123); \ DO_TESTCASE_6I(desc, name, 132); \ DO_TESTCASE_6I(desc, name, 213); \ DO_TESTCASE_6I(desc, name, 231); \ DO_TESTCASE_6I(desc, name, 312); \ DO_TESTCASE_6I(desc, name, 321); #define DO_TESTCASE_6x6RW(desc, name) \ DO_TESTCASE_6IRW(desc, name, 123); \ DO_TESTCASE_6IRW(desc, name, 132); \ DO_TESTCASE_6IRW(desc, name, 213); \ DO_TESTCASE_6IRW(desc, name, 231); \ DO_TESTCASE_6IRW(desc, name, 312); \ DO_TESTCASE_6IRW(desc, name, 321); static void ww_test_fail_acquire(void) { int ret; WWAI(&t); t.stamp++; ret = WWL(&o, &t); if (WARN_ON(!o.ctx) || WARN_ON(ret)) return; /* No lockdep test, pure API */ ret = WWL(&o, &t); WARN_ON(ret != -EALREADY); ret = WWT(&o); WARN_ON(ret); t2 = t; t2.stamp++; ret = WWL(&o, &t2); WARN_ON(ret != -EDEADLK); WWU(&o); if (WWT(&o)) WWU(&o); #ifdef CONFIG_DEBUG_LOCK_ALLOC else DEBUG_LOCKS_WARN_ON(1); #endif } static void ww_test_normal(void) { int ret; WWAI(&t); /* * None of the ww_mutex codepaths should be taken in the 'normal' * mutex calls. The easiest way to verify this is by using the * normal mutex calls, and making sure o.ctx is unmodified. */ /* mutex_lock (and indirectly, mutex_lock_nested) */ o.ctx = (void *)~0UL; mutex_lock(&o.base); mutex_unlock(&o.base); WARN_ON(o.ctx != (void *)~0UL); /* mutex_lock_interruptible (and *_nested) */ o.ctx = (void *)~0UL; ret = mutex_lock_interruptible(&o.base); if (!ret) mutex_unlock(&o.base); else WARN_ON(1); WARN_ON(o.ctx != (void *)~0UL); /* mutex_lock_killable (and *_nested) */ o.ctx = (void *)~0UL; ret = mutex_lock_killable(&o.base); if (!ret) mutex_unlock(&o.base); else WARN_ON(1); WARN_ON(o.ctx != (void *)~0UL); /* trylock, succeeding */ o.ctx = (void *)~0UL; ret = mutex_trylock(&o.base); WARN_ON(!ret); if (ret) mutex_unlock(&o.base); else WARN_ON(1); WARN_ON(o.ctx != (void *)~0UL); /* trylock, failing */ o.ctx = (void *)~0UL; mutex_lock(&o.base); ret = mutex_trylock(&o.base); WARN_ON(ret); mutex_unlock(&o.base); WARN_ON(o.ctx != (void *)~0UL); /* nest_lock */ o.ctx = (void *)~0UL; mutex_lock_nest_lock(&o.base, &t); mutex_unlock(&o.base); WARN_ON(o.ctx != (void *)~0UL); } static void ww_test_two_contexts(void) { WWAI(&t); WWAI(&t2); } static void ww_test_diff_class(void) { WWAI(&t); #ifdef CONFIG_DEBUG_MUTEXES t.ww_class = NULL; #endif WWL(&o, &t); } static void ww_test_context_done_twice(void) { WWAI(&t); WWAD(&t); WWAD(&t); WWAF(&t); } static void ww_test_context_unlock_twice(void) { WWAI(&t); WWAD(&t); WWAF(&t); WWAF(&t); } static void ww_test_context_fini_early(void) { WWAI(&t); WWL(&o, &t); WWAD(&t); WWAF(&t); } static void ww_test_context_lock_after_done(void) { WWAI(&t); WWAD(&t); WWL(&o, &t); } static void ww_test_object_unlock_twice(void) { WWL1(&o); WWU(&o); WWU(&o); } static void ww_test_object_lock_unbalanced(void) { WWAI(&t); WWL(&o, &t); t.acquired = 0; WWU(&o); WWAF(&t); } static void ww_test_object_lock_stale_context(void) { WWAI(&t); o.ctx = &t2; WWL(&o, &t); } static void ww_test_edeadlk_normal(void) { int ret; mutex_lock(&o2.base); o2.ctx = &t2; mutex_release(&o2.base.dep_map, 1, _THIS_IP_); WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); o2.ctx = NULL; mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); mutex_unlock(&o2.base); WWU(&o); WWL(&o2, &t); } static void ww_test_edeadlk_normal_slow(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); o2.ctx = NULL; mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); mutex_unlock(&o2.base); WWU(&o); ww_mutex_lock_slow(&o2, &t); } static void ww_test_edeadlk_no_unlock(void) { int ret; mutex_lock(&o2.base); o2.ctx = &t2; mutex_release(&o2.base.dep_map, 1, _THIS_IP_); WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); o2.ctx = NULL; mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); mutex_unlock(&o2.base); WWL(&o2, &t); } static void ww_test_edeadlk_no_unlock_slow(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); o2.ctx = NULL; mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); mutex_unlock(&o2.base); ww_mutex_lock_slow(&o2, &t); } static void ww_test_edeadlk_acquire_more(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); ret = WWL(&o3, &t); } static void ww_test_edeadlk_acquire_more_slow(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); ww_mutex_lock_slow(&o3, &t); } static void ww_test_edeadlk_acquire_more_edeadlk(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; mutex_lock(&o3.base); mutex_release(&o3.base.dep_map, 1, _THIS_IP_); o3.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); ret = WWL(&o3, &t); WARN_ON(ret != -EDEADLK); } static void ww_test_edeadlk_acquire_more_edeadlk_slow(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; mutex_lock(&o3.base); mutex_release(&o3.base.dep_map, 1, _THIS_IP_); o3.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); ww_mutex_lock_slow(&o3, &t); } static void ww_test_edeadlk_acquire_wrong(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); if (!ret) WWU(&o2); WWU(&o); ret = WWL(&o3, &t); } static void ww_test_edeadlk_acquire_wrong_slow(void) { int ret; mutex_lock(&o2.base); mutex_release(&o2.base.dep_map, 1, _THIS_IP_); o2.ctx = &t2; WWAI(&t); t2 = t; t2.stamp--; ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret != -EDEADLK); if (!ret) WWU(&o2); WWU(&o); ww_mutex_lock_slow(&o3, &t); } static void ww_test_spin_nest_unlocked(void) { raw_spin_lock_nest_lock(&lock_A, &o.base); U(A); } static void ww_test_unneeded_slow(void) { WWAI(&t); ww_mutex_lock_slow(&o, &t); } static void ww_test_context_block(void) { int ret; WWAI(&t); ret = WWL(&o, &t); WARN_ON(ret); WWL1(&o2); } static void ww_test_context_try(void) { int ret; WWAI(&t); ret = WWL(&o, &t); WARN_ON(ret); ret = WWT(&o2); WARN_ON(!ret); WWU(&o2); WWU(&o); } static void ww_test_context_context(void) { int ret; WWAI(&t); ret = WWL(&o, &t); WARN_ON(ret); ret = WWL(&o2, &t); WARN_ON(ret); WWU(&o2); WWU(&o); } static void ww_test_try_block(void) { bool ret; ret = WWT(&o); WARN_ON(!ret); WWL1(&o2); WWU(&o2); WWU(&o); } static void ww_test_try_try(void) { bool ret; ret = WWT(&o); WARN_ON(!ret); ret = WWT(&o2); WARN_ON(!ret); WWU(&o2); WWU(&o); } static void ww_test_try_context(void) { int ret; ret = WWT(&o); WARN_ON(!ret); WWAI(&t); ret = WWL(&o2, &t); WARN_ON(ret); } static void ww_test_block_block(void) { WWL1(&o); WWL1(&o2); } static void ww_test_block_try(void) { bool ret; WWL1(&o); ret = WWT(&o2); WARN_ON(!ret); } static void ww_test_block_context(void) { int ret; WWL1(&o); WWAI(&t); ret = WWL(&o2, &t); WARN_ON(ret); } static void ww_test_spin_block(void) { L(A); U(A); WWL1(&o); L(A); U(A); WWU(&o); L(A); WWL1(&o); WWU(&o); U(A); } static void ww_test_spin_try(void) { bool ret; L(A); U(A); ret = WWT(&o); WARN_ON(!ret); L(A); U(A); WWU(&o); L(A); ret = WWT(&o); WARN_ON(!ret); WWU(&o); U(A); } static void ww_test_spin_context(void) { int ret; L(A); U(A); WWAI(&t); ret = WWL(&o, &t); WARN_ON(ret); L(A); U(A); WWU(&o); L(A); ret = WWL(&o, &t); WARN_ON(ret); WWU(&o); U(A); } static void ww_tests(void) { printk(" --------------------------------------------------------------------------\n"); printk(" | Wound/wait tests |\n"); printk(" ---------------------\n"); print_testname("ww api failures"); dotest(ww_test_fail_acquire, SUCCESS, LOCKTYPE_WW); dotest(ww_test_normal, SUCCESS, LOCKTYPE_WW); dotest(ww_test_unneeded_slow, FAILURE, LOCKTYPE_WW); pr_cont("\n"); print_testname("ww contexts mixing"); dotest(ww_test_two_contexts, FAILURE, LOCKTYPE_WW); dotest(ww_test_diff_class, FAILURE, LOCKTYPE_WW); pr_cont("\n"); print_testname("finishing ww context"); dotest(ww_test_context_done_twice, FAILURE, LOCKTYPE_WW); dotest(ww_test_context_unlock_twice, FAILURE, LOCKTYPE_WW); dotest(ww_test_context_fini_early, FAILURE, LOCKTYPE_WW); dotest(ww_test_context_lock_after_done, FAILURE, LOCKTYPE_WW); pr_cont("\n"); print_testname("locking mismatches"); dotest(ww_test_object_unlock_twice, FAILURE, LOCKTYPE_WW); dotest(ww_test_object_lock_unbalanced, FAILURE, LOCKTYPE_WW); dotest(ww_test_object_lock_stale_context, FAILURE, LOCKTYPE_WW); pr_cont("\n"); print_testname("EDEADLK handling"); dotest(ww_test_edeadlk_normal, SUCCESS, LOCKTYPE_WW); dotest(ww_test_edeadlk_normal_slow, SUCCESS, LOCKTYPE_WW); dotest(ww_test_edeadlk_no_unlock, FAILURE, LOCKTYPE_WW); dotest(ww_test_edeadlk_no_unlock_slow, FAILURE, LOCKTYPE_WW); dotest(ww_test_edeadlk_acquire_more, FAILURE, LOCKTYPE_WW); dotest(ww_test_edeadlk_acquire_more_slow, FAILURE, LOCKTYPE_WW); dotest(ww_test_edeadlk_acquire_more_edeadlk, FAILURE, LOCKTYPE_WW); dotest(ww_test_edeadlk_acquire_more_edeadlk_slow, FAILURE, LOCKTYPE_WW); dotest(ww_test_edeadlk_acquire_wrong, FAILURE, LOCKTYPE_WW); dotest(ww_test_edeadlk_acquire_wrong_slow, FAILURE, LOCKTYPE_WW); pr_cont("\n"); print_testname("spinlock nest unlocked"); dotest(ww_test_spin_nest_unlocked, FAILURE, LOCKTYPE_WW); pr_cont("\n"); printk(" -----------------------------------------------------\n"); printk(" |block | try |context|\n"); printk(" -----------------------------------------------------\n"); print_testname("context"); dotest(ww_test_context_block, FAILURE, LOCKTYPE_WW); dotest(ww_test_context_try, SUCCESS, LOCKTYPE_WW); dotest(ww_test_context_context, SUCCESS, LOCKTYPE_WW); pr_cont("\n"); print_testname("try"); dotest(ww_test_try_block, FAILURE, LOCKTYPE_WW); dotest(ww_test_try_try, SUCCESS, LOCKTYPE_WW); dotest(ww_test_try_context, FAILURE, LOCKTYPE_WW); pr_cont("\n"); print_testname("block"); dotest(ww_test_block_block, FAILURE, LOCKTYPE_WW); dotest(ww_test_block_try, SUCCESS, LOCKTYPE_WW); dotest(ww_test_block_context, FAILURE, LOCKTYPE_WW); pr_cont("\n"); print_testname("spinlock"); dotest(ww_test_spin_block, FAILURE, LOCKTYPE_WW); dotest(ww_test_spin_try, SUCCESS, LOCKTYPE_WW); dotest(ww_test_spin_context, FAILURE, LOCKTYPE_WW); pr_cont("\n"); } void locking_selftest(void) { /* * Got a locking failure before the selftest ran? */ if (!debug_locks) { printk("----------------------------------\n"); printk("| Locking API testsuite disabled |\n"); printk("----------------------------------\n"); return; } /* * Run the testsuite: */ printk("------------------------\n"); printk("| Locking API testsuite:\n"); printk("----------------------------------------------------------------------------\n"); printk(" | spin |wlock |rlock |mutex | wsem | rsem |\n"); printk(" --------------------------------------------------------------------------\n"); init_shared_classes(); debug_locks_silent = !debug_locks_verbose; DO_TESTCASE_6R("A-A deadlock", AA); DO_TESTCASE_6R("A-B-B-A deadlock", ABBA); DO_TESTCASE_6R("A-B-B-C-C-A deadlock", ABBCCA); DO_TESTCASE_6R("A-B-C-A-B-C deadlock", ABCABC); DO_TESTCASE_6R("A-B-B-C-C-D-D-A deadlock", ABBCCDDA); DO_TESTCASE_6R("A-B-C-D-B-D-D-A deadlock", ABCDBDDA); DO_TESTCASE_6R("A-B-C-D-B-C-D-A deadlock", ABCDBCDA); DO_TESTCASE_6("double unlock", double_unlock); DO_TESTCASE_6("initialize held", init_held); printk(" --------------------------------------------------------------------------\n"); print_testname("recursive read-lock"); pr_cont(" |"); dotest(rlock_AA1, SUCCESS, LOCKTYPE_RWLOCK); pr_cont(" |"); dotest(rsem_AA1, FAILURE, LOCKTYPE_RWSEM); pr_cont("\n"); print_testname("recursive read-lock #2"); pr_cont(" |"); dotest(rlock_AA1B, SUCCESS, LOCKTYPE_RWLOCK); pr_cont(" |"); dotest(rsem_AA1B, FAILURE, LOCKTYPE_RWSEM); pr_cont("\n"); print_testname("mixed read-write-lock"); pr_cont(" |"); dotest(rlock_AA2, FAILURE, LOCKTYPE_RWLOCK); pr_cont(" |"); dotest(rsem_AA2, FAILURE, LOCKTYPE_RWSEM); pr_cont("\n"); print_testname("mixed write-read-lock"); pr_cont(" |"); dotest(rlock_AA3, FAILURE, LOCKTYPE_RWLOCK); pr_cont(" |"); dotest(rsem_AA3, FAILURE, LOCKTYPE_RWSEM); pr_cont("\n"); print_testname("mixed read-lock/lock-write ABBA"); pr_cont(" |"); dotest(rlock_ABBA1, FAILURE, LOCKTYPE_RWLOCK); #ifdef CONFIG_PROVE_LOCKING /* * Lockdep does indeed fail here, but there's nothing we can do about * that now. Don't kill lockdep for it. */ unexpected_testcase_failures--; #endif pr_cont(" |"); dotest(rwsem_ABBA1, FAILURE, LOCKTYPE_RWSEM); print_testname("mixed read-lock/lock-read ABBA"); pr_cont(" |"); dotest(rlock_ABBA2, SUCCESS, LOCKTYPE_RWLOCK); pr_cont(" |"); dotest(rwsem_ABBA2, FAILURE, LOCKTYPE_RWSEM); print_testname("mixed write-lock/lock-write ABBA"); pr_cont(" |"); dotest(rlock_ABBA3, FAILURE, LOCKTYPE_RWLOCK); pr_cont(" |"); dotest(rwsem_ABBA3, FAILURE, LOCKTYPE_RWSEM); printk(" --------------------------------------------------------------------------\n"); /* * irq-context testcases: */ DO_TESTCASE_2x6("irqs-on + irq-safe-A", irqsafe1); DO_TESTCASE_2x3("sirq-safe-A => hirqs-on", irqsafe2A); DO_TESTCASE_2x6("safe-A + irqs-on", irqsafe2B); DO_TESTCASE_6x6("safe-A + unsafe-B #1", irqsafe3); DO_TESTCASE_6x6("safe-A + unsafe-B #2", irqsafe4); DO_TESTCASE_6x6RW("irq lock-inversion", irq_inversion); DO_TESTCASE_6x2("irq read-recursion", irq_read_recursion); // DO_TESTCASE_6x2B("irq read-recursion #2", irq_read_recursion2); ww_tests(); if (unexpected_testcase_failures) { printk("-----------------------------------------------------------------\n"); debug_locks = 0; printk("BUG: %3d unexpected failures (out of %3d) - debugging disabled! |\n", unexpected_testcase_failures, testcase_total); printk("-----------------------------------------------------------------\n"); } else if (expected_testcase_failures && testcase_successes) { printk("--------------------------------------------------------\n"); printk("%3d out of %3d testcases failed, as expected. |\n", expected_testcase_failures, testcase_total); printk("----------------------------------------------------\n"); debug_locks = 1; } else if (expected_testcase_failures && !testcase_successes) { printk("--------------------------------------------------------\n"); printk("All %3d testcases failed, as expected. |\n", expected_testcase_failures); printk("----------------------------------------\n"); debug_locks = 1; } else { printk("-------------------------------------------------------\n"); printk("Good, all %3d testcases passed! |\n", testcase_successes); printk("---------------------------------\n"); debug_locks = 1; } debug_locks_silent = 0; } 1189'>1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 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/*
 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
 *  Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
 *
 *  Bugs:
 *     - sometimes record brokes playback with WSS portion of
 *       Yamaha OPL3-SA3 chip
 *     - CS4231 (GUS MAX) - still trouble with occasional noises
 *			  - broken initialization?
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/wss.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>

#include <asm/io.h>
#include <asm/dma.h>
#include <asm/irq.h>

MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
MODULE_LICENSE("GPL");

#if 0
#define SNDRV_DEBUG_MCE
#endif

/*
 *  Some variables
 */

static unsigned char freq_bits[14] = {
	/* 5510 */	0x00 | CS4231_XTAL2,
	/* 6620 */	0x0E | CS4231_XTAL2,
	/* 8000 */	0x00 | CS4231_XTAL1,
	/* 9600 */	0x0E | CS4231_XTAL1,
	/* 11025 */	0x02 | CS4231_XTAL2,
	/* 16000 */	0x02 | CS4231_XTAL1,
	/* 18900 */	0x04 | CS4231_XTAL2,
	/* 22050 */	0x06 | CS4231_XTAL2,
	/* 27042 */	0x04 | CS4231_XTAL1,
	/* 32000 */	0x06 | CS4231_XTAL1,
	/* 33075 */	0x0C | CS4231_XTAL2,
	/* 37800 */	0x08 | CS4231_XTAL2,
	/* 44100 */	0x0A | CS4231_XTAL2,
	/* 48000 */	0x0C | CS4231_XTAL1
};

static unsigned int rates[14] = {
	5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
	27042, 32000, 33075, 37800, 44100, 48000
};

static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
	.count = ARRAY_SIZE(rates),
	.list = rates,
	.mask = 0,
};

static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
{
	return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
					  &hw_constraints_rates);
}

static unsigned char snd_wss_original_image[32] =
{
	0x00,			/* 00/00 - lic */
	0x00,			/* 01/01 - ric */
	0x9f,			/* 02/02 - la1ic */
	0x9f,			/* 03/03 - ra1ic */
	0x9f,			/* 04/04 - la2ic */
	0x9f,			/* 05/05 - ra2ic */
	0xbf,			/* 06/06 - loc */
	0xbf,			/* 07/07 - roc */
	0x20,			/* 08/08 - pdfr */
	CS4231_AUTOCALIB,	/* 09/09 - ic */
	0x00,			/* 0a/10 - pc */
	0x00,			/* 0b/11 - ti */
	CS4231_MODE2,		/* 0c/12 - mi */
	0xfc,			/* 0d/13 - lbc */
	0x00,			/* 0e/14 - pbru */
	0x00,			/* 0f/15 - pbrl */
	0x80,			/* 10/16 - afei */
	0x01,			/* 11/17 - afeii */
	0x9f,			/* 12/18 - llic */
	0x9f,			/* 13/19 - rlic */
	0x00,			/* 14/20 - tlb */
	0x00,			/* 15/21 - thb */
	0x00,			/* 16/22 - la3mic/reserved */
	0x00,			/* 17/23 - ra3mic/reserved */
	0x00,			/* 18/24 - afs */
	0x00,			/* 19/25 - lamoc/version */
	0xcf,			/* 1a/26 - mioc */
	0x00,			/* 1b/27 - ramoc/reserved */
	0x20,			/* 1c/28 - cdfr */
	0x00,			/* 1d/29 - res4 */
	0x00,			/* 1e/30 - cbru */
	0x00,			/* 1f/31 - cbrl */
};

static unsigned char snd_opti93x_original_image[32] =
{
	0x00,		/* 00/00 - l_mixout_outctrl */
	0x00,		/* 01/01 - r_mixout_outctrl */
	0x88,		/* 02/02 - l_cd_inctrl */
	0x88,		/* 03/03 - r_cd_inctrl */
	0x88,		/* 04/04 - l_a1/fm_inctrl */
	0x88,		/* 05/05 - r_a1/fm_inctrl */
	0x80,		/* 06/06 - l_dac_inctrl */
	0x80,		/* 07/07 - r_dac_inctrl */
	0x00,		/* 08/08 - ply_dataform_reg */
	0x00,		/* 09/09 - if_conf */
	0x00,		/* 0a/10 - pin_ctrl */
	0x00,		/* 0b/11 - err_init_reg */
	0x0a,		/* 0c/12 - id_reg */
	0x00,		/* 0d/13 - reserved */
	0x00,		/* 0e/14 - ply_upcount_reg */
	0x00,		/* 0f/15 - ply_lowcount_reg */
	0x88,		/* 10/16 - reserved/l_a1_inctrl */
	0x88,		/* 11/17 - reserved/r_a1_inctrl */
	0x88,		/* 12/18 - l_line_inctrl */
	0x88,		/* 13/19 - r_line_inctrl */
	0x88,		/* 14/20 - l_mic_inctrl */
	0x88,		/* 15/21 - r_mic_inctrl */
	0x80,		/* 16/22 - l_out_outctrl */
	0x80,		/* 17/23 - r_out_outctrl */
	0x00,		/* 18/24 - reserved */
	0x00,		/* 19/25 - reserved */
	0x00,		/* 1a/26 - reserved */
	0x00,		/* 1b/27 - reserved */
	0x00,		/* 1c/28 - cap_dataform_reg */
	0x00,		/* 1d/29 - reserved */
	0x00,		/* 1e/30 - cap_upcount_reg */
	0x00		/* 1f/31 - cap_lowcount_reg */
};

/*
 *  Basic I/O functions
 */

static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
{
	outb(val, chip->port + offset);
}

static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
{
	return inb(chip->port + offset);
}

static void snd_wss_wait(struct snd_wss *chip)
{
	int timeout;

	for (timeout = 250;
	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
	     timeout--)
		udelay(100);
}

static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
			 unsigned char value)
{
	int timeout;

	for (timeout = 250;
	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
	     timeout--)
		udelay(10);
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
	wss_outb(chip, CS4231P(REG), value);
	mb();
}

void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
{
	snd_wss_wait(chip);
#ifdef CONFIG_SND_DEBUG
	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
		snd_printk(KERN_DEBUG "out: auto calibration time out "
			   "- reg = 0x%x, value = 0x%x\n", reg, value);
#endif
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
	wss_outb(chip, CS4231P(REG), value);
	chip->image[reg] = value;
	mb();
	snd_printdd("codec out - reg 0x%x = 0x%x\n",
			chip->mce_bit | reg, value);
}
EXPORT_SYMBOL(snd_wss_out);

unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
{
	snd_wss_wait(chip);
#ifdef CONFIG_SND_DEBUG
	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
		snd_printk(KERN_DEBUG "in: auto calibration time out "
			   "- reg = 0x%x\n", reg);
#endif
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
	mb();
	return wss_inb(chip, CS4231P(REG));
}
EXPORT_SYMBOL(snd_wss_in);

void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
			unsigned char val)
{
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
	wss_outb(chip, CS4231P(REG),
		 reg | (chip->image[CS4236_EXT_REG] & 0x01));
	wss_outb(chip, CS4231P(REG), val);
	chip->eimage[CS4236_REG(reg)] = val;
#if 0
	printk(KERN_DEBUG "ext out : reg = 0x%x, val = 0x%x\n", reg, val);
#endif
}
EXPORT_SYMBOL(snd_cs4236_ext_out);

unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
{
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
	wss_outb(chip, CS4231P(REG),
		 reg | (chip->image[CS4236_EXT_REG] & 0x01));
#if 1
	return wss_inb(chip, CS4231P(REG));
#else
	{
		unsigned char res;
		res = wss_inb(chip, CS4231P(REG));
		printk(KERN_DEBUG "ext in : reg = 0x%x, val = 0x%x\n",
		       reg, res);
		return res;
	}
#endif
}
EXPORT_SYMBOL(snd_cs4236_ext_in);

#if 0

static void snd_wss_debug(struct snd_wss *chip)
{
	printk(KERN_DEBUG
		"CS4231 REGS:      INDEX = 0x%02x  "
		"                 STATUS = 0x%02x\n",
					wss_inb(chip, CS4231P(REGSEL)),
					wss_inb(chip, CS4231P(STATUS)));
	printk(KERN_DEBUG
		"  0x00: left input      = 0x%02x  "
		"  0x10: alt 1 (CFIG 2)  = 0x%02x\n",
					snd_wss_in(chip, 0x00),
					snd_wss_in(chip, 0x10));
	printk(KERN_DEBUG
		"  0x01: right input     = 0x%02x  "
		"  0x11: alt 2 (CFIG 3)  = 0x%02x\n",
					snd_wss_in(chip, 0x01),
					snd_wss_in(chip, 0x11));
	printk(KERN_DEBUG
		"  0x02: GF1 left input  = 0x%02x  "
		"  0x12: left line in    = 0x%02x\n",
					snd_wss_in(chip, 0x02),
					snd_wss_in(chip, 0x12));
	printk(KERN_DEBUG
		"  0x03: GF1 right input = 0x%02x  "
		"  0x13: right line in   = 0x%02x\n",
					snd_wss_in(chip, 0x03),
					snd_wss_in(chip, 0x13));
	printk(KERN_DEBUG
		"  0x04: CD left input   = 0x%02x  "
		"  0x14: timer low       = 0x%02x\n",
					snd_wss_in(chip, 0x04),
					snd_wss_in(chip, 0x14));
	printk(KERN_DEBUG
		"  0x05: CD right input  = 0x%02x  "
		"  0x15: timer high      = 0x%02x\n",
					snd_wss_in(chip, 0x05),
					snd_wss_in(chip, 0x15));
	printk(KERN_DEBUG
		"  0x06: left output     = 0x%02x  "
		"  0x16: left MIC (PnP)  = 0x%02x\n",
					snd_wss_in(chip, 0x06),
					snd_wss_in(chip, 0x16));
	printk(KERN_DEBUG
		"  0x07: right output    = 0x%02x  "
		"  0x17: right MIC (PnP) = 0x%02x\n",
					snd_wss_in(chip, 0x07),
					snd_wss_in(chip, 0x17));
	printk(KERN_DEBUG
		"  0x08: playback format = 0x%02x  "
		"  0x18: IRQ status      = 0x%02x\n",
					snd_wss_in(chip, 0x08),
					snd_wss_in(chip, 0x18));
	printk(KERN_DEBUG
		"  0x09: iface (CFIG 1)  = 0x%02x  "
		"  0x19: left line out   = 0x%02x\n",
					snd_wss_in(chip, 0x09),
					snd_wss_in(chip, 0x19));
	printk(KERN_DEBUG
		"  0x0a: pin control     = 0x%02x  "
		"  0x1a: mono control    = 0x%02x\n",
					snd_wss_in(chip, 0x0a),
					snd_wss_in(chip, 0x1a));
	printk(KERN_DEBUG
		"  0x0b: init & status   = 0x%02x  "
		"  0x1b: right line out  = 0x%02x\n",
					snd_wss_in(chip, 0x0b),
					snd_wss_in(chip, 0x1b));
	printk(KERN_DEBUG
		"  0x0c: revision & mode = 0x%02x  "
		"  0x1c: record format   = 0x%02x\n",
					snd_wss_in(chip, 0x0c),
					snd_wss_in(chip, 0x1c));
	printk(KERN_DEBUG
		"  0x0d: loopback        = 0x%02x  "
		"  0x1d: var freq (PnP)  = 0x%02x\n",
					snd_wss_in(chip, 0x0d),
					snd_wss_in(chip, 0x1d));
	printk(KERN_DEBUG
		"  0x0e: ply upr count   = 0x%02x  "
		"  0x1e: ply lwr count   = 0x%02x\n",
					snd_wss_in(chip, 0x0e),
					snd_wss_in(chip, 0x1e));
	printk(KERN_DEBUG
		"  0x0f: rec upr count   = 0x%02x  "
		"  0x1f: rec lwr count   = 0x%02x\n",
					snd_wss_in(chip, 0x0f),
					snd_wss_in(chip, 0x1f));
}

#endif

/*
 *  CS4231 detection / MCE routines
 */

static void snd_wss_busy_wait(struct snd_wss *chip)
{
	int timeout;

	/* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
	for (timeout = 5; timeout > 0; timeout--)
		wss_inb(chip, CS4231P(REGSEL));
	/* end of cleanup sequence */
	for (timeout = 25000;
	     timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
	     timeout--)
		udelay(10);
}

void snd_wss_mce_up(struct snd_wss *chip)
{
	unsigned long flags;
	int timeout;

	snd_wss_wait(chip);
#ifdef CONFIG_SND_DEBUG
	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
		snd_printk(KERN_DEBUG
			   "mce_up - auto calibration time out (0)\n");
#endif
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->mce_bit |= CS4231_MCE;
	timeout = wss_inb(chip, CS4231P(REGSEL));
	if (timeout == 0x80)
		snd_printk(KERN_DEBUG "mce_up [0x%lx]: "
			   "serious init problem - codec still busy\n",
			   chip->port);
	if (!(timeout & CS4231_MCE))
		wss_outb(chip, CS4231P(REGSEL),
			 chip->mce_bit | (timeout & 0x1f));
	spin_unlock_irqrestore(&chip->reg_lock, flags);
}
EXPORT_SYMBOL(snd_wss_mce_up);

void snd_wss_mce_down(struct snd_wss *chip)
{
	unsigned long flags;
	unsigned long end_time;
	int timeout;
	int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;

	snd_wss_busy_wait(chip);

#ifdef CONFIG_SND_DEBUG
	if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
		snd_printk(KERN_DEBUG "mce_down [0x%lx] - "
			   "auto calibration time out (0)\n",
			   (long)CS4231P(REGSEL));
#endif
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->mce_bit &= ~CS4231_MCE;
	timeout = wss_inb(chip, CS4231P(REGSEL));
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	if (timeout == 0x80)
		snd_printk(KERN_DEBUG "mce_down [0x%lx]: "
			   "serious init problem - codec still busy\n",
			   chip->port);
	if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
		return;

	/*
	 * Wait for (possible -- during init auto-calibration may not be set)
	 * calibration process to start. Needs up to 5 sample periods on AD1848
	 * which at the slowest possible rate of 5.5125 kHz means 907 us.
	 */
	msleep(1);

	snd_printdd("(1) jiffies = %lu\n", jiffies);

	/* check condition up to 250 ms */
	end_time = jiffies + msecs_to_jiffies(250);
	while (snd_wss_in(chip, CS4231_TEST_INIT) &
		CS4231_CALIB_IN_PROGRESS) {

		if (time_after(jiffies, end_time)) {
			snd_printk(KERN_ERR "mce_down - "
					"auto calibration time out (2)\n");
			return;
		}
		msleep(1);
	}

	snd_printdd("(2) jiffies = %lu\n", jiffies);

	/* check condition up to 100 ms */
	end_time = jiffies + msecs_to_jiffies(100);
	while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
		if (time_after(jiffies, end_time)) {
			snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
			return;
		}
		msleep(1);
	}

	snd_printdd("(3) jiffies = %lu\n", jiffies);
	snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
}
EXPORT_SYMBOL(snd_wss_mce_down);

static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
{
	switch (format & 0xe0) {
	case CS4231_LINEAR_16:
	case CS4231_LINEAR_16_BIG:
		size >>= 1;
		break;
	case CS4231_ADPCM_16:
		return size >> 2;
	}
	if (format & CS4231_STEREO)
		size >>= 1;
	return size;
}

static int snd_wss_trigger(struct snd_pcm_substream *substream,
			   int cmd)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	int result = 0;
	unsigned int what;
	struct snd_pcm_substream *s;
	int do_start;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
		do_start = 1; break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		do_start = 0; break;
	default:
		return -EINVAL;
	}

	what = 0;
	snd_pcm_group_for_each_entry(s, substream) {
		if (s == chip->playback_substream) {
			what |= CS4231_PLAYBACK_ENABLE;
			snd_pcm_trigger_done(s, substream);
		} else if (s == chip->capture_substream) {
			what |= CS4231_RECORD_ENABLE;
			snd_pcm_trigger_done(s, substream);
		}
	}
	spin_lock(&chip->reg_lock);
	if (do_start) {
		chip->image[CS4231_IFACE_CTRL] |= what;
		if (chip->trigger)
			chip->trigger(chip, what, 1);
	} else {
		chip->image[CS4231_IFACE_CTRL] &= ~what;
		if (chip->trigger)
			chip->trigger(chip, what, 0);
	}
	snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
	spin_unlock(&chip->reg_lock);
#if 0
	snd_wss_debug(chip);
#endif
	return result;
}

/*
 *  CODEC I/O
 */

static unsigned char snd_wss_get_rate(unsigned int rate)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(rates); i++)
		if (rate == rates[i])
			return freq_bits[i];
	// snd_BUG();
	return freq_bits[ARRAY_SIZE(rates) - 1];
}

static unsigned char snd_wss_get_format(struct snd_wss *chip,
					int format,
					int channels)
{
	unsigned char rformat;

	rformat = CS4231_LINEAR_8;
	switch (format) {
	case SNDRV_PCM_FORMAT_MU_LAW:	rformat = CS4231_ULAW_8; break;
	case SNDRV_PCM_FORMAT_A_LAW:	rformat = CS4231_ALAW_8; break;
	case SNDRV_PCM_FORMAT_S16_LE:	rformat = CS4231_LINEAR_16; break;
	case SNDRV_PCM_FORMAT_S16_BE:	rformat = CS4231_LINEAR_16_BIG; break;
	case SNDRV_PCM_FORMAT_IMA_ADPCM:	rformat = CS4231_ADPCM_16; break;
	}
	if (channels > 1)
		rformat |= CS4231_STEREO;
#if 0
	snd_printk(KERN_DEBUG "get_format: 0x%x (mode=0x%x)\n", format, mode);
#endif
	return rformat;
}

static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
{
	unsigned long flags;

	mute = mute ? 0x80 : 0;
	spin_lock_irqsave(&chip->reg_lock, flags);
	if (chip->calibrate_mute == mute) {
		spin_unlock_irqrestore(&chip->reg_lock, flags);
		return;
	}
	if (!mute) {
		snd_wss_dout(chip, CS4231_LEFT_INPUT,
			     chip->image[CS4231_LEFT_INPUT]);
		snd_wss_dout(chip, CS4231_RIGHT_INPUT,
			     chip->image[CS4231_RIGHT_INPUT]);
		snd_wss_dout(chip, CS4231_LOOPBACK,
			     chip->image[CS4231_LOOPBACK]);
	} else {
		snd_wss_dout(chip, CS4231_LEFT_INPUT,
			     0);
		snd_wss_dout(chip, CS4231_RIGHT_INPUT,
			     0);
		snd_wss_dout(chip, CS4231_LOOPBACK,
			     0xfd);
	}

	snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
		     mute | chip->image[CS4231_AUX1_LEFT_INPUT]);
	snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
		     mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);
	snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
		     mute | chip->image[CS4231_AUX2_LEFT_INPUT]);
	snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
		     mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);
	snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
		     mute | chip->image[CS4231_LEFT_OUTPUT]);
	snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
		     mute | chip->image[CS4231_RIGHT_OUTPUT]);
	if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
		snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
			     mute | chip->image[CS4231_LEFT_LINE_IN]);
		snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
			     mute | chip->image[CS4231_RIGHT_LINE_IN]);
		snd_wss_dout(chip, CS4231_MONO_CTRL,
			     mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
	}
	if (chip->hardware == WSS_HW_INTERWAVE) {
		snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
			     mute | chip->image[CS4231_LEFT_MIC_INPUT]);
		snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
			     mute | chip->image[CS4231_RIGHT_MIC_INPUT]);
		snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
			     mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);
		snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
			     mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);
	}
	chip->calibrate_mute = mute;
	spin_unlock_irqrestore(&chip->reg_lock, flags);
}

static void snd_wss_playback_format(struct snd_wss *chip,
				       struct snd_pcm_hw_params *params,
				       unsigned char pdfr)
{
	unsigned long flags;
	int full_calib = 1;

	mutex_lock(&chip->mce_mutex);
	if (chip->hardware == WSS_HW_CS4231A ||
	    (chip->hardware & WSS_HW_CS4232_MASK)) {
		spin_lock_irqsave(&chip->reg_lock, flags);
		if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) {	/* rate is same? */
			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				    chip->image[CS4231_ALT_FEATURE_1] | 0x10);
			chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
			snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
				    chip->image[CS4231_PLAYBK_FORMAT]);
			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				    chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
			udelay(100); /* Fixes audible clicks at least on GUS MAX */
			full_calib = 0;
		}
		spin_unlock_irqrestore(&chip->reg_lock, flags);
	} else if (chip->hardware == WSS_HW_AD1845) {
		unsigned rate = params_rate(params);

		/*
		 * Program the AD1845 correctly for the playback stream.
		 * Note that we do NOT need to toggle the MCE bit because
		 * the PLAYBACK_ENABLE bit of the Interface Configuration
		 * register is set.
		 *
		 * NOTE: We seem to need to write to the MSB before the LSB
		 *       to get the correct sample frequency.
		 */
		spin_lock_irqsave(&chip->reg_lock, flags);
		snd_wss_out(chip, CS4231_PLAYBK_FORMAT, (pdfr & 0xf0));
		snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
		snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
		full_calib = 0;
		spin_unlock_irqrestore(&chip->reg_lock, flags);
	}
	if (full_calib) {
		snd_wss_mce_up(chip);
		spin_lock_irqsave(&chip->reg_lock, flags);
		if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
			if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
				pdfr = (pdfr & 0xf0) |
				       (chip->image[CS4231_REC_FORMAT] & 0x0f);
		} else {
			chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
		}
		snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
		spin_unlock_irqrestore(&chip->reg_lock, flags);
		if (chip->hardware == WSS_HW_OPL3SA2)
			udelay(100);	/* this seems to help */
		snd_wss_mce_down(chip);
	}
	mutex_unlock(&chip->mce_mutex);
}

static void snd_wss_capture_format(struct snd_wss *chip,
				   struct snd_pcm_hw_params *params,
				   unsigned char cdfr)
{
	unsigned long flags;
	int full_calib = 1;

	mutex_lock(&chip->mce_mutex);
	if (chip->hardware == WSS_HW_CS4231A ||
	    (chip->hardware & WSS_HW_CS4232_MASK)) {
		spin_lock_irqsave(&chip->reg_lock, flags);
		if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) ||	/* rate is same? */
		    (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				chip->image[CS4231_ALT_FEATURE_1] | 0x20);
			snd_wss_out(chip, CS4231_REC_FORMAT,
				chip->image[CS4231_REC_FORMAT] = cdfr);
			snd_wss_out(chip, CS4231_ALT_FEATURE_1,
				chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
			full_calib = 0;
		}
		spin_unlock_irqrestore(&chip->reg_lock, flags);
	} else if (chip->hardware == WSS_HW_AD1845) {
		unsigned rate = params_rate(params);

		/*
		 * Program the AD1845 correctly for the capture stream.
		 * Note that we do NOT need to toggle the MCE bit because
		 * the PLAYBACK_ENABLE bit of the Interface Configuration
		 * register is set.
		 *
		 * NOTE: We seem to need to write to the MSB before the LSB
		 *       to get the correct sample frequency.
		 */
		spin_lock_irqsave(&chip->reg_lock, flags);
		snd_wss_out(chip, CS4231_REC_FORMAT, (cdfr & 0xf0));
		snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
		snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
		full_calib = 0;
		spin_unlock_irqrestore(&chip->reg_lock, flags);
	}
	if (full_calib) {
		snd_wss_mce_up(chip);
		spin_lock_irqsave(&chip->reg_lock, flags);
		if (chip->hardware != WSS_HW_INTERWAVE &&
		    !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
			if (chip->single_dma)
				snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
			else
				snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
				   (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
				   (cdfr & 0x0f));
			spin_unlock_irqrestore(&chip->reg_lock, flags);
			snd_wss_mce_down(chip);
			snd_wss_mce_up(chip);
			spin_lock_irqsave(&chip->reg_lock, flags);
		}
		if (chip->hardware & WSS_HW_AD1848_MASK)
			snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
		else
			snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
		spin_unlock_irqrestore(&chip->reg_lock, flags);
		snd_wss_mce_down(chip);
	}
	mutex_unlock(&chip->mce_mutex);
}

/*
 *  Timer interface
 */

static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
{
	struct snd_wss *chip = snd_timer_chip(timer);
	if (chip->hardware & WSS_HW_CS4236B_MASK)
		return 14467;
	else
		return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
}

static int snd_wss_timer_start(struct snd_timer *timer)
{
	unsigned long flags;
	unsigned int ticks;
	struct snd_wss *chip = snd_timer_chip(timer);
	spin_lock_irqsave(&chip->reg_lock, flags);
	ticks = timer->sticks;
	if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
	    (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
	    (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
		chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
		snd_wss_out(chip, CS4231_TIMER_HIGH,
			    chip->image[CS4231_TIMER_HIGH]);
		chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
		snd_wss_out(chip, CS4231_TIMER_LOW,
			    chip->image[CS4231_TIMER_LOW]);
		snd_wss_out(chip, CS4231_ALT_FEATURE_1,
			    chip->image[CS4231_ALT_FEATURE_1] |
			    CS4231_TIMER_ENABLE);
	}
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	return 0;
}

static int snd_wss_timer_stop(struct snd_timer *timer)
{
	unsigned long flags;
	struct snd_wss *chip = snd_timer_chip(timer);
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
	snd_wss_out(chip, CS4231_ALT_FEATURE_1,
		    chip->image[CS4231_ALT_FEATURE_1]);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	return 0;
}

static void snd_wss_init(struct snd_wss *chip)
{
	unsigned long flags;

	snd_wss_calibrate_mute(chip, 1);
	snd_wss_mce_down(chip);

#ifdef SNDRV_DEBUG_MCE
	snd_printk(KERN_DEBUG "init: (1)\n");
#endif
	snd_wss_mce_up(chip);
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
					    CS4231_PLAYBACK_PIO |
					    CS4231_RECORD_ENABLE |
					    CS4231_RECORD_PIO |
					    CS4231_CALIB_MODE);
	chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
	snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	snd_wss_mce_down(chip);

#ifdef SNDRV_DEBUG_MCE
	snd_printk(KERN_DEBUG "init: (2)\n");
#endif

	snd_wss_mce_up(chip);
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->image[CS4231_IFACE_CTRL] &= ~CS4231_AUTOCALIB;
	snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
	snd_wss_out(chip,
		    CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	snd_wss_mce_down(chip);

#ifdef SNDRV_DEBUG_MCE
	snd_printk(KERN_DEBUG "init: (3) - afei = 0x%x\n",
		   chip->image[CS4231_ALT_FEATURE_1]);
#endif

	spin_lock_irqsave(&chip->reg_lock, flags);
	snd_wss_out(chip, CS4231_ALT_FEATURE_2,
		    chip->image[CS4231_ALT_FEATURE_2]);
	spin_unlock_irqrestore(&chip->reg_lock, flags);

	snd_wss_mce_up(chip);
	spin_lock_irqsave(&chip->reg_lock, flags);
	snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
		    chip->image[CS4231_PLAYBK_FORMAT]);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	snd_wss_mce_down(chip);

#ifdef SNDRV_DEBUG_MCE
	snd_printk(KERN_DEBUG "init: (4)\n");
#endif

	snd_wss_mce_up(chip);
	spin_lock_irqsave(&chip->reg_lock, flags);
	if (!(chip->hardware & WSS_HW_AD1848_MASK))
		snd_wss_out(chip, CS4231_REC_FORMAT,
			    chip->image[CS4231_REC_FORMAT]);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	snd_wss_mce_down(chip);
	snd_wss_calibrate_mute(chip, 0);

#ifdef SNDRV_DEBUG_MCE
	snd_printk(KERN_DEBUG "init: (5)\n");
#endif
}

static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
{
	unsigned long flags;

	mutex_lock(&chip->open_mutex);
	if ((chip->mode & mode) ||
	    ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
		mutex_unlock(&chip->open_mutex);
		return -EAGAIN;
	}
	if (chip->mode & WSS_MODE_OPEN) {
		chip->mode |= mode;
		mutex_unlock(&chip->open_mutex);
		return 0;
	}
	/* ok. now enable and ack CODEC IRQ */
	spin_lock_irqsave(&chip->reg_lock, flags);
	if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
		snd_wss_out(chip, CS4231_IRQ_STATUS,
			    CS4231_PLAYBACK_IRQ |
			    CS4231_RECORD_IRQ |
			    CS4231_TIMER_IRQ);
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
	}
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
	snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
	if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
		snd_wss_out(chip, CS4231_IRQ_STATUS,
			    CS4231_PLAYBACK_IRQ |
			    CS4231_RECORD_IRQ |
			    CS4231_TIMER_IRQ);
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
	}
	spin_unlock_irqrestore(&chip->reg_lock, flags);

	chip->mode = mode;
	mutex_unlock(&chip->open_mutex);
	return 0;
}

static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
{
	unsigned long flags;

	mutex_lock(&chip->open_mutex);
	chip->mode &= ~mode;
	if (chip->mode & WSS_MODE_OPEN) {
		mutex_unlock(&chip->open_mutex);
		return;
	}
	/* disable IRQ */
	spin_lock_irqsave(&chip->reg_lock, flags);
	if (!(chip->hardware & WSS_HW_AD1848_MASK))
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
	snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);

	/* now disable record & playback */

	if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
					       CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
		spin_unlock_irqrestore(&chip->reg_lock, flags);
		snd_wss_mce_up(chip);
		spin_lock_irqsave(&chip->reg_lock, flags);
		chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
						     CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
		snd_wss_out(chip, CS4231_IFACE_CTRL,
			    chip->image[CS4231_IFACE_CTRL]);
		spin_unlock_irqrestore(&chip->reg_lock, flags);
		snd_wss_mce_down(chip);
		spin_lock_irqsave(&chip->reg_lock, flags);
	}

	/* clear IRQ again */
	if (!(chip->hardware & WSS_HW_AD1848_MASK))
		snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	wss_outb(chip, CS4231P(STATUS), 0);	/* clear IRQ */
	spin_unlock_irqrestore(&chip->reg_lock, flags);

	chip->mode = 0;
	mutex_unlock(&chip->open_mutex);
}

/*
 *  timer open/close
 */

static int snd_wss_timer_open(struct snd_timer *timer)
{
	struct snd_wss *chip = snd_timer_chip(timer);
	snd_wss_open(chip, WSS_MODE_TIMER);
	return 0;
}

static int snd_wss_timer_close(struct snd_timer *timer)
{
	struct snd_wss *chip = snd_timer_chip(timer);
	snd_wss_close(chip, WSS_MODE_TIMER);
	return 0;
}

static struct snd_timer_hardware snd_wss_timer_table =
{
	.flags =	SNDRV_TIMER_HW_AUTO,
	.resolution =	9945,
	.ticks =	65535,
	.open =		snd_wss_timer_open,
	.close =	snd_wss_timer_close,
	.c_resolution = snd_wss_timer_resolution,
	.start =	snd_wss_timer_start,
	.stop =		snd_wss_timer_stop,
};

/*
 *  ok.. exported functions..
 */

static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
					 struct snd_pcm_hw_params *hw_params)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	unsigned char new_pdfr;
	int err;

	if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
		return err;
	new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
				params_channels(hw_params)) |
				snd_wss_get_rate(params_rate(hw_params));
	chip->set_playback_format(chip, hw_params, new_pdfr);
	return 0;
}

static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
{
	return snd_pcm_lib_free_pages(substream);
}

static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
	unsigned long flags;
	unsigned int size = snd_pcm_lib_buffer_bytes(substream);
	unsigned int count = snd_pcm_lib_period_bytes(substream);

	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->p_dma_size = size;
	chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
	snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
	count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
	snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
	snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
	spin_unlock_irqrestore(&chip->reg_lock, flags);
#if 0
	snd_wss_debug(chip);
#endif
	return 0;
}

static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
					struct snd_pcm_hw_params *hw_params)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	unsigned char new_cdfr;
	int err;

	if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
		return err;
	new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
			   params_channels(hw_params)) |
			   snd_wss_get_rate(params_rate(hw_params));
	chip->set_capture_format(chip, hw_params, new_cdfr);
	return 0;
}

static int snd_wss_capture_hw_free(struct snd_pcm_substream *substream)
{
	return snd_pcm_lib_free_pages(substream);
}

static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
	unsigned long flags;
	unsigned int size = snd_pcm_lib_buffer_bytes(substream);
	unsigned int count = snd_pcm_lib_period_bytes(substream);

	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->c_dma_size = size;
	chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
	snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
	if (chip->hardware & WSS_HW_AD1848_MASK)
		count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
					  count);
	else
		count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
					  count);
	count--;
	if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
		snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
		snd_wss_out(chip, CS4231_PLY_UPR_CNT,
			    (unsigned char) (count >> 8));
	} else {
		snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
		snd_wss_out(chip, CS4231_REC_UPR_CNT,
			    (unsigned char) (count >> 8));
	}
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	return 0;
}

void snd_wss_overrange(struct snd_wss *chip)
{
	unsigned long flags;
	unsigned char res;

	spin_lock_irqsave(&chip->reg_lock, flags);
	res = snd_wss_in(chip, CS4231_TEST_INIT);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	if (res & (0x08 | 0x02))	/* detect overrange only above 0dB; may be user selectable? */
		chip->capture_substream->runtime->overrange++;
}
EXPORT_SYMBOL(snd_wss_overrange);

irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
{
	struct snd_wss *chip = dev_id;
	unsigned char status;

	if (chip->hardware & WSS_HW_AD1848_MASK)
		/* pretend it was the only possible irq for AD1848 */
		status = CS4231_PLAYBACK_IRQ;
	else
		status = snd_wss_in(chip, CS4231_IRQ_STATUS);
	if (status & CS4231_TIMER_IRQ) {
		if (chip->timer)
			snd_timer_interrupt(chip->timer, chip->timer->sticks);
	}
	if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
		if (status & CS4231_PLAYBACK_IRQ) {
			if (chip->mode & WSS_MODE_PLAY) {
				if (chip->playback_substream)
					snd_pcm_period_elapsed(chip->playback_substream);
			}
			if (chip->mode & WSS_MODE_RECORD) {
				if (chip->capture_substream) {
					snd_wss_overrange(chip);
					snd_pcm_period_elapsed(chip->capture_substream);
				}
			}
		}
	} else {
		if (status & CS4231_PLAYBACK_IRQ) {
			if (chip->playback_substream)
				snd_pcm_period_elapsed(chip->playback_substream);
		}
		if (status & CS4231_RECORD_IRQ) {
			if (chip->capture_substream) {
				snd_wss_overrange(chip);
				snd_pcm_period_elapsed(chip->capture_substream);
			}
		}
	}

	spin_lock(&chip->reg_lock);
	status = ~CS4231_ALL_IRQS | ~status;
	if (chip->hardware & WSS_HW_AD1848_MASK)
		wss_outb(chip, CS4231P(STATUS), 0);
	else
		snd_wss_out(chip, CS4231_IRQ_STATUS, status);
	spin_unlock(&chip->reg_lock);
	return IRQ_HANDLED;
}
EXPORT_SYMBOL(snd_wss_interrupt);

static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	size_t ptr;

	if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
		return 0;
	ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
	return bytes_to_frames(substream->runtime, ptr);
}

static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	size_t ptr;

	if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
		return 0;
	ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
	return bytes_to_frames(substream->runtime, ptr);
}

/*

 */

static int snd_ad1848_probe(struct snd_wss *chip)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
	unsigned long flags;
	unsigned char r;
	unsigned short hardware = 0;
	int err = 0;
	int i;

	while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
		if (time_after(jiffies, timeout))
			return -ENODEV;
		cond_resched();
	}
	spin_lock_irqsave(&chip->reg_lock, flags);

	/* set CS423x MODE 1 */
	snd_wss_dout(chip, CS4231_MISC_INFO, 0);

	snd_wss_dout(chip, CS4231_RIGHT_INPUT, 0x45); /* 0x55 & ~0x10 */
	r = snd_wss_in(chip, CS4231_RIGHT_INPUT);
	if (r != 0x45) {
		/* RMGE always high on AD1847 */
		if ((r & ~CS4231_ENABLE_MIC_GAIN) != 0x45) {
			err = -ENODEV;
			goto out;
		}
		hardware = WSS_HW_AD1847;
	} else {
		snd_wss_dout(chip, CS4231_LEFT_INPUT,  0xaa);
		r = snd_wss_in(chip, CS4231_LEFT_INPUT);
		/* L/RMGE always low on AT2320 */
		if ((r | CS4231_ENABLE_MIC_GAIN) != 0xaa) {
			err = -ENODEV;
			goto out;
		}
	}

	/* clear pending IRQ */
	wss_inb(chip, CS4231P(STATUS));
	wss_outb(chip, CS4231P(STATUS), 0);
	mb();

	if ((chip->hardware & WSS_HW_TYPE_MASK) != WSS_HW_DETECT)
		goto out;

	if (hardware) {
		chip->hardware = hardware;
		goto out;
	}

	r = snd_wss_in(chip, CS4231_MISC_INFO);

	/* set CS423x MODE 2 */
	snd_wss_dout(chip, CS4231_MISC_INFO, CS4231_MODE2);
	for (i = 0; i < 16; i++) {
		if (snd_wss_in(chip, i) != snd_wss_in(chip, 16 + i)) {
			/* we have more than 16 registers: check ID */
			if ((r & 0xf) != 0xa)
				goto out_mode;
			/*
			 * on CMI8330, CS4231_VERSION is volume control and
			 * can be set to 0
			 */
			snd_wss_dout(chip, CS4231_VERSION, 0);
			r = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
			if (!r)
				chip->hardware = WSS_HW_CMI8330;
			goto out_mode;
		}
	}
	if (r & 0x80)
		chip->hardware = WSS_HW_CS4248;
	else
		chip->hardware = WSS_HW_AD1848;
out_mode:
	snd_wss_dout(chip, CS4231_MISC_INFO, 0);
out:
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	return err;
}

static int snd_wss_probe(struct snd_wss *chip)
{
	unsigned long flags;
	int i, id, rev, regnum;
	unsigned char *ptr;
	unsigned int hw;

	id = snd_ad1848_probe(chip);
	if (id < 0)
		return id;

	hw = chip->hardware;
	if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
		for (i = 0; i < 50; i++) {
			mb();
			if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
				msleep(2);
			else {
				spin_lock_irqsave(&chip->reg_lock, flags);
				snd_wss_out(chip, CS4231_MISC_INFO,
					    CS4231_MODE2);
				id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
				spin_unlock_irqrestore(&chip->reg_lock, flags);
				if (id == 0x0a)
					break;	/* this is valid value */
			}
		}
		snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
		if (id != 0x0a)
			return -ENODEV;	/* no valid device found */

		rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
		snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
		if (rev == 0x80) {
			unsigned char tmp = snd_wss_in(chip, 23);
			snd_wss_out(chip, 23, ~tmp);
			if (snd_wss_in(chip, 23) != tmp)
				chip->hardware = WSS_HW_AD1845;
			else
				chip->hardware = WSS_HW_CS4231;
		} else if (rev == 0xa0) {
			chip->hardware = WSS_HW_CS4231A;
		} else if (rev == 0xa2) {
			chip->hardware = WSS_HW_CS4232;
		} else if (rev == 0xb2) {
			chip->hardware = WSS_HW_CS4232A;
		} else if (rev == 0x83) {
			chip->hardware = WSS_HW_CS4236;
		} else if (rev == 0x03) {
			chip->hardware = WSS_HW_CS4236B;
		} else {
			snd_printk(KERN_ERR
				   "unknown CS chip with version 0x%x\n", rev);
			return -ENODEV;		/* unknown CS4231 chip? */
		}
	}
	spin_lock_irqsave(&chip->reg_lock, flags);
	wss_inb(chip, CS4231P(STATUS));	/* clear any pendings IRQ */
	wss_outb(chip, CS4231P(STATUS), 0);
	mb();
	spin_unlock_irqrestore(&chip->reg_lock, flags);

	if (!(chip->hardware & WSS_HW_AD1848_MASK))
		chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
	switch (chip->hardware) {
	case WSS_HW_INTERWAVE:
		chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
		break;
	case WSS_HW_CS4235:
	case WSS_HW_CS4236B:
	case WSS_HW_CS4237B:
	case WSS_HW_CS4238B:
	case WSS_HW_CS4239:
		if (hw == WSS_HW_DETECT3)
			chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
		else
			chip->hardware = WSS_HW_CS4236;
		break;
	}

	chip->image[CS4231_IFACE_CTRL] =
	    (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
	    (chip->single_dma ? CS4231_SINGLE_DMA : 0);
	if (chip->hardware != WSS_HW_OPTI93X) {
		chip->image[CS4231_ALT_FEATURE_1] = 0x80;
		chip->image[CS4231_ALT_FEATURE_2] =
			chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
	}
	/* enable fine grained frequency selection */
	if (chip->hardware == WSS_HW_AD1845)
		chip->image[AD1845_PWR_DOWN] = 8;

	ptr = (unsigned char *) &chip->image;
	regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
	snd_wss_mce_down(chip);
	spin_lock_irqsave(&chip->reg_lock, flags);
	for (i = 0; i < regnum; i++)	/* ok.. fill all registers */
		snd_wss_out(chip, i, *ptr++);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	snd_wss_mce_up(chip);
	snd_wss_mce_down(chip);

	mdelay(2);

	/* ok.. try check hardware version for CS4236+ chips */
	if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
		if (chip->hardware == WSS_HW_CS4236B) {
			rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
			snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
			id = snd_cs4236_ext_in(chip, CS4236_VERSION);
			snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
			snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
			if ((id & 0x1f) == 0x1d) {	/* CS4235 */
				chip->hardware = WSS_HW_CS4235;
				switch (id >> 5) {
				case 4:
				case 5:
				case 6:
					break;
				default:
					snd_printk(KERN_WARNING
						"unknown CS4235 chip "
						"(enhanced version = 0x%x)\n",
						id);
				}
			} else if ((id & 0x1f) == 0x0b) {	/* CS4236/B */
				switch (id >> 5) {
				case 4:
				case 5:
				case 6:
				case 7:
					chip->hardware = WSS_HW_CS4236B;
					break;
				default:
					snd_printk(KERN_WARNING
						"unknown CS4236 chip "
						"(enhanced version = 0x%x)\n",
						id);
				}
			} else if ((id & 0x1f) == 0x08) {	/* CS4237B */
				chip->hardware = WSS_HW_CS4237B;
				switch (id >> 5) {
				case 4:
				case 5:
				case 6:
				case 7:
					break;
				default:
					snd_printk(KERN_WARNING
						"unknown CS4237B chip "
						"(enhanced version = 0x%x)\n",
						id);
				}
			} else if ((id & 0x1f) == 0x09) {	/* CS4238B */
				chip->hardware = WSS_HW_CS4238B;
				switch (id >> 5) {
				case 5:
				case 6:
				case 7:
					break;
				default:
					snd_printk(KERN_WARNING
						"unknown CS4238B chip "
						"(enhanced version = 0x%x)\n",
						id);
				}
			} else if ((id & 0x1f) == 0x1e) {	/* CS4239 */
				chip->hardware = WSS_HW_CS4239;
				switch (id >> 5) {
				case 4:
				case 5:
				case 6:
					break;
				default:
					snd_printk(KERN_WARNING
						"unknown CS4239 chip "
						"(enhanced version = 0x%x)\n",
						id);
				}
			} else {
				snd_printk(KERN_WARNING
					   "unknown CS4236/CS423xB chip "
					   "(enhanced version = 0x%x)\n", id);
			}
		}
	}
	return 0;		/* all things are ok.. */
}

/*

 */

static struct snd_pcm_hardware snd_wss_playback =
{
	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
				 SNDRV_PCM_INFO_MMAP_VALID |
				 SNDRV_PCM_INFO_SYNC_START),
	.formats =		(SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
				 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
	.rates =		SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
	.rate_min =		5510,
	.rate_max =		48000,
	.channels_min =		1,
	.channels_max =		2,
	.buffer_bytes_max =	(128*1024),
	.period_bytes_min =	64,
	.period_bytes_max =	(128*1024),
	.periods_min =		1,
	.periods_max =		1024,
	.fifo_size =		0,
};

static struct snd_pcm_hardware snd_wss_capture =
{
	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
				 SNDRV_PCM_INFO_MMAP_VALID |
				 SNDRV_PCM_INFO_RESUME |
				 SNDRV_PCM_INFO_SYNC_START),
	.formats =		(SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
				 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
	.rates =		SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
	.rate_min =		5510,
	.rate_max =		48000,
	.channels_min =		1,
	.channels_max =		2,
	.buffer_bytes_max =	(128*1024),
	.period_bytes_min =	64,
	.period_bytes_max =	(128*1024),
	.periods_min =		1,
	.periods_max =		1024,
	.fifo_size =		0,
};

/*

 */

static int snd_wss_playback_open(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
	int err;

	runtime->hw = snd_wss_playback;

	/* hardware limitation of older chipsets */
	if (chip->hardware & WSS_HW_AD1848_MASK)
		runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
					 SNDRV_PCM_FMTBIT_S16_BE);

	/* hardware bug in InterWave chipset */
	if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
		runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;

	/* hardware limitation of cheap chips */
	if (chip->hardware == WSS_HW_CS4235 ||
	    chip->hardware == WSS_HW_CS4239)
		runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;

	snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
	snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);

	if (chip->claim_dma) {
		if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
			return err;
	}

	err = snd_wss_open(chip, WSS_MODE_PLAY);
	if (err < 0) {
		if (chip->release_dma)
			chip->release_dma(chip, chip->dma_private_data, chip->dma1);
		snd_free_pages(runtime->dma_area, runtime->dma_bytes);
		return err;
	}
	chip->playback_substream = substream;
	snd_pcm_set_sync(substream);
	chip->rate_constraint(runtime);
	return 0;
}

static int snd_wss_capture_open(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
	int err;

	runtime->hw = snd_wss_capture;

	/* hardware limitation of older chipsets */
	if (chip->hardware & WSS_HW_AD1848_MASK)
		runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
					 SNDRV_PCM_FMTBIT_S16_BE);

	/* hardware limitation of cheap chips */
	if (chip->hardware == WSS_HW_CS4235 ||
	    chip->hardware == WSS_HW_CS4239 ||
	    chip->hardware == WSS_HW_OPTI93X)
		runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |
				      SNDRV_PCM_FMTBIT_S16_LE;

	snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
	snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);

	if (chip->claim_dma) {
		if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
			return err;
	}

	err = snd_wss_open(chip, WSS_MODE_RECORD);
	if (err < 0) {
		if (chip->release_dma)
			chip->release_dma(chip, chip->dma_private_data, chip->dma2);
		snd_free_pages(runtime->dma_area, runtime->dma_bytes);
		return err;
	}
	chip->capture_substream = substream;
	snd_pcm_set_sync(substream);
	chip->rate_constraint(runtime);
	return 0;
}

static int snd_wss_playback_close(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);

	chip->playback_substream = NULL;
	snd_wss_close(chip, WSS_MODE_PLAY);
	return 0;
}

static int snd_wss_capture_close(struct snd_pcm_substream *substream)
{
	struct snd_wss *chip = snd_pcm_substream_chip(substream);

	chip->capture_substream = NULL;
	snd_wss_close(chip, WSS_MODE_RECORD);
	return 0;
}

static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
{
	int tmp;

	if (!chip->thinkpad_flag)
		return;

	outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
	tmp = inb(AD1848_THINKPAD_CTL_PORT2);

	if (on)
		/* turn it on */
		tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
	else
		/* turn it off */
		tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;

	outb(tmp, AD1848_THINKPAD_CTL_PORT2);
}

#ifdef CONFIG_PM

/* lowlevel suspend callback for CS4231 */
static void snd_wss_suspend(struct snd_wss *chip)
{
	int reg;
	unsigned long flags;

	snd_pcm_suspend_all(chip->pcm);
	spin_lock_irqsave(&chip->reg_lock, flags);
	for (reg = 0; reg < 32; reg++)
		chip->image[reg] = snd_wss_in(chip, reg);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	if (chip->thinkpad_flag)
		snd_wss_thinkpad_twiddle(chip, 0);
}

/* lowlevel resume callback for CS4231 */
static void snd_wss_resume(struct snd_wss *chip)
{
	int reg;
	unsigned long flags;
	/* int timeout; */

	if (chip->thinkpad_flag)
		snd_wss_thinkpad_twiddle(chip, 1);
	snd_wss_mce_up(chip);
	spin_lock_irqsave(&chip->reg_lock, flags);
	for (reg = 0; reg < 32; reg++) {
		switch (reg) {
		case CS4231_VERSION:
			break;
		default:
			snd_wss_out(chip, reg, chip->image[reg]);
			break;
		}
	}
	/* Yamaha needs this to resume properly */
	if (chip->hardware == WSS_HW_OPL3SA2)
		snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
			    chip->image[CS4231_PLAYBK_FORMAT]);
	spin_unlock_irqrestore(&chip->reg_lock, flags);
#if 1
	snd_wss_mce_down(chip);
#else
	/* The following is a workaround to avoid freeze after resume on TP600E.
	   This is the first half of copy of snd_wss_mce_down(), but doesn't
	   include rescheduling.  -- iwai
	   */
	snd_wss_busy_wait(chip);
	spin_lock_irqsave(&chip->reg_lock, flags);
	chip->mce_bit &= ~CS4231_MCE;
	timeout = wss_inb(chip, CS4231P(REGSEL));
	wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	if (timeout == 0x80)
		snd_printk(KERN_ERR "down [0x%lx]: serious init problem "
			   "- codec still busy\n", chip->port);
	if ((timeout & CS4231_MCE) == 0 ||
	    !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
		return;
	}
	snd_wss_busy_wait(chip);
#endif
}
#endif /* CONFIG_PM */

static int snd_wss_free(struct snd_wss *chip)
{
	release_and_free_resource(chip->res_port);
	release_and_free_resource(chip->res_cport);
	if (chip->irq >= 0) {
		disable_irq(chip->irq);
		if (!(chip->hwshare & WSS_HWSHARE_IRQ))
			free_irq(chip->irq, (void *) chip);
	}
	if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
		snd_dma_disable(chip->dma1);
		free_dma(chip->dma1);
	}
	if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
	    chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
		snd_dma_disable(chip->dma2);
		free_dma(chip->dma2);
	}
	if (chip->timer)
		snd_device_free(chip->card, chip->timer);
	kfree(chip);
	return 0;
}

static int snd_wss_dev_free(struct snd_device *device)
{
	struct snd_wss *chip = device->device_data;
	return snd_wss_free(chip);
}

const char *snd_wss_chip_id(struct snd_wss *chip)
{
	switch (chip->hardware) {
	case WSS_HW_CS4231:
		return "CS4231";
	case WSS_HW_CS4231A:
		return "CS4231A";
	case WSS_HW_CS4232:
		return "CS4232";
	case WSS_HW_CS4232A:
		return "CS4232A";
	case WSS_HW_CS4235:
		return "CS4235";
	case WSS_HW_CS4236:
		return "CS4236";
	case WSS_HW_CS4236B:
		return "CS4236B";
	case WSS_HW_CS4237B:
		return "CS4237B";
	case WSS_HW_CS4238B:
		return "CS4238B";
	case WSS_HW_CS4239:
		return "CS4239";
	case WSS_HW_INTERWAVE:
		return "AMD InterWave";
	case WSS_HW_OPL3SA2:
		return chip->card->shortname;
	case WSS_HW_AD1845:
		return "AD1845";
	case WSS_HW_OPTI93X:
		return "OPTi 93x";
	case WSS_HW_AD1847:
		return "AD1847";
	case WSS_HW_AD1848:
		return "AD1848";
	case WSS_HW_CS4248:
		return "CS4248";
	case WSS_HW_CMI8330:
		return "CMI8330/C3D";
	default:
		return "???";
	}
}
EXPORT_SYMBOL(snd_wss_chip_id);

static int snd_wss_new(struct snd_card *card,
			  unsigned short hardware,
			  unsigned short hwshare,
			  struct snd_wss **rchip)
{
	struct snd_wss *chip;

	*rchip = NULL;
	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;
	chip->hardware = hardware;
	chip->hwshare = hwshare;

	spin_lock_init(&chip->reg_lock);
	mutex_init(&chip->mce_mutex);
	mutex_init(&chip->open_mutex);
	chip->card = card;
	chip->rate_constraint = snd_wss_xrate;
	chip->set_playback_format = snd_wss_playback_format;
	chip->set_capture_format = snd_wss_capture_format;
	if (chip->hardware == WSS_HW_OPTI93X)
		memcpy(&chip->image, &snd_opti93x_original_image,
		       sizeof(snd_opti93x_original_image));
	else
		memcpy(&chip->image, &snd_wss_original_image,
		       sizeof(snd_wss_original_image));
	if (chip->hardware & WSS_HW_AD1848_MASK) {
		chip->image[CS4231_PIN_CTRL] = 0;
		chip->image[CS4231_TEST_INIT] = 0;
	}

	*rchip = chip;
	return 0;
}

int snd_wss_create(struct snd_card *card,
		      unsigned long port,
		      unsigned long cport,
		      int irq, int dma1, int dma2,
		      unsigned short hardware,
		      unsigned short hwshare,
		      struct snd_wss **rchip)
{
	static struct snd_device_ops ops = {
		.dev_free =	snd_wss_dev_free,
	};
	struct snd_wss *chip;
	int err;

	err = snd_wss_new(card, hardware, hwshare, &chip);
	if (err < 0)
		return err;

	chip->irq = -1;
	chip->dma1 = -1;
	chip->dma2 = -1;

	chip->res_port = request_region(port, 4, "WSS");
	if (!chip->res_port) {
		snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
		snd_wss_free(chip);
		return -EBUSY;
	}
	chip->port = port;
	if ((long)cport >= 0) {
		chip->res_cport = request_region(cport, 8, "CS4232 Control");
		if (!chip->res_cport) {
			snd_printk(KERN_ERR
				"wss: can't grab control port 0x%lx\n", cport);
			snd_wss_free(chip);
			return -ENODEV;
		}
	}
	chip->cport = cport;
	if (!(hwshare & WSS_HWSHARE_IRQ))
		if (request_irq(irq, snd_wss_interrupt, 0,
				"WSS", (void *) chip)) {
			snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
			snd_wss_free(chip);
			return -EBUSY;
		}
	chip->irq = irq;
	if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
		snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
		snd_wss_free(chip);
		return -EBUSY;
	}
	chip->dma1 = dma1;