#ifndef QDEV_H #define QDEV_H #include "hw.h" #include "qemu-queue.h" #include "qemu-char.h" #include "qemu-option.h" #include "qapi/qapi-visit-core.h" #include "qemu/object.h" #include "error.h" typedef struct Property Property; typedef struct PropertyInfo PropertyInfo; typedef struct CompatProperty CompatProperty; typedef struct BusState BusState; typedef struct BusClass BusClass; enum DevState { DEV_STATE_CREATED = 1, DEV_STATE_INITIALIZED, }; enum { DEV_NVECTORS_UNSPECIFIED = -1, }; #define TYPE_DEVICE "device" #define DEVICE(obj) OBJECT_CHECK(DeviceState, (obj), TYPE_DEVICE) #define DEVICE_CLASS(klass) OBJECT_CLASS_CHECK(DeviceClass, (klass), TYPE_DEVICE) #define DEVICE_GET_CLASS(obj) OBJECT_GET_CLASS(DeviceClass, (obj), TYPE_DEVICE) typedef int (*qdev_initfn)(DeviceState *dev); typedef int (*qdev_event)(DeviceState *dev); typedef void (*qdev_resetfn)(DeviceState *dev); typedef struct DeviceClass { ObjectClass parent_class; const char *fw_name; const char *desc; Property *props; int no_user; /* callbacks */ void (*reset)(DeviceState *dev); /* device state */ const VMStateDescription *vmsd; /* Private to qdev / bus. */ qdev_initfn init; qdev_event unplug; qdev_event exit; const char *bus_type; } DeviceClass; /* This structure should not be accessed directly. We declare it here so that it can be embedded in individual device state structures. */ struct DeviceState { Object parent_obj; const char *id; enum DevState state; QemuOpts *opts; int hotplugged; BusState *parent_bus; int num_gpio_out; qemu_irq *gpio_out; int num_gpio_in; qemu_irq *gpio_in; QLIST_HEAD(, BusState) child_bus; int num_child_bus; int instance_id_alias; int alias_required_for_version; }; #define TYPE_BUS "bus" #define BUS(obj) OBJECT_CHECK(BusState, (obj), TYPE_BUS) #define BUS_CLASS(klass) OBJECT_CLASS_CHECK(BusClass, (klass), TYPE_BUS) #define BUS_GET_CLASS(obj) OBJECT_GET_CLASS(BusClass, (obj), TYPE_BUS) struct BusClass { ObjectClass parent_class; /* FIXME first arg should be BusState */ void (*print_dev)(Monitor *mon, DeviceState *dev, int indent); char *(*get_dev_path)(DeviceState *dev); /* * This callback is used to create Open Firmware device path in accordance * with OF spec http://forthworks.com/standards/of1275.pdf. Individual bus * bindings can be found at http://playground.sun.com/1275/bindings/. */ char *(*get_fw_dev_path)(DeviceState *dev); int (*reset)(BusState *bus); }; typedef struct BusChild { DeviceState *child; int index; QTAILQ_ENTRY(BusChild) sibling; } BusChild; /** * BusState: * @qom_allocated: Indicates whether the object was allocated by QOM. * @glib_allocated: Indicates whether the object was initialized in-place * yet is expected to be freed with g_free(). */ struct BusState { Object obj; DeviceState *parent; const char *name; int allow_hotplug; bool qom_allocated; bool glib_allocated; int max_index; QTAILQ_HEAD(ChildrenHead, BusChild) children; QLIST_ENTRY(BusState) sibling; }; struct Property { const char *name; PropertyInfo *info; int offset; uint8_t bitnr; uint8_t qtype; int64_t defval; }; struct PropertyInfo { const char *name; const char *legacy_name; const char **enum_table; int (*parse)(DeviceState *dev, Property *prop, const char *str); int (*print)(DeviceState *dev, Property *prop, char *dest, size_t len); ObjectPropertyAccessor *get; ObjectPropertyAccessor *set; ObjectPropertyRelease *release; }; typedef struct GlobalProperty { const char *driver; const char *property; const char *value; QTAILQ_ENTRY(GlobalProperty) next; } GlobalProperty; /*** Board API. This should go away once we have a machine config file. ***/ DeviceState *qdev_create(BusState *bus, const char *name); DeviceState *qdev_try_create(BusState *bus, const char *name); bool qdev_exists(const char *name); int qdev_device_help(QemuOpts *opts); DeviceState *qdev_device_add(QemuOpts *opts); int qdev_init(DeviceState *dev) QEMU_WARN_UNUSED_RESULT; void qdev_init_nofail(DeviceState *dev); void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, int required_for_version); void qdev_unplug(DeviceState *dev, Error **errp); void qdev_free(DeviceState *dev); int qdev_simple_unplug_cb(DeviceState *dev); void qdev_machine_creation_done(void); bool qdev_machine_modified(void); qemu_irq qdev_get_gpio_in(DeviceState *dev, int n); void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); BusState *qdev_get_child_bus(DeviceState *dev, const char *name); /*** Device API. ***/ /* Register device properties. */ /* GPIO inputs also double as IRQ sinks. */ void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); BusState *qdev_get_parent_bus(DeviceState *dev); /*** BUS API. ***/ DeviceState *qdev_find_recursive(BusState *bus, const char *id); /* Returns 0 to walk children, > 0 to skip walk, < 0 to terminate walk. */ typedef int (qbus_walkerfn)(BusState *bus, void *opaque); typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque); void qbus_create_inplace(BusState *bus, const char *typename, DeviceState *parent, const char *name); BusState *qbus_create(const char *typename, DeviceState *parent, const char *name); /* Returns > 0 if either devfn or busfn skip walk somewhere in cursion, * < 0 if either devfn or busfn terminate walk somewhere in cursion, * 0 otherwise. */ int qbus_walk_children(BusState *bus, qdev_walkerfn *devfn, qbus_walkerfn *busfn, void *opaque); int qdev_walk_children(DeviceState *dev, qdev_walkerfn *devfn, qbus_walkerfn *busfn, void *opaque); void qdev_reset_all(DeviceState *dev); void qbus_reset_all_fn(void *opaque); void qbus_free(BusState *bus); #define FROM_QBUS(type, dev) DO_UPCAST(type, qbus, dev) /* This should go away once we get rid of the NULL bus hack */ BusState *sysbus_get_default(void); /*** monitor commands ***/ void do_info_qtree(Monitor *mon); void do_info_qdm(Monitor *mon); int do_device_add(Monitor *mon, const QDict *qdict, QObject **ret_data); int do_device_del(Monitor *mon, const QDict *qdict, QObject **ret_data); /*** qdev-properties.c ***/ extern PropertyInfo qdev_prop_bit; extern PropertyInfo qdev_prop_uint8; extern PropertyInfo qdev_prop_uint16; extern PropertyInfo qdev_prop_uint32; extern PropertyInfo qdev_prop_int32; extern PropertyInfo qdev_prop_uint64; extern PropertyInfo qdev_prop_hex8; extern PropertyInfo qdev_prop_hex32; extern PropertyInfo qdev_prop_hex64; extern PropertyInfo qdev_prop_string; extern PropertyInfo qdev_prop_chr; extern PropertyInfo qdev_prop_ptr; extern PropertyInfo qdev_prop_macaddr; extern PropertyInfo qdev_prop_losttickpolicy; extern PropertyInfo qdev_prop_bios_chs_trans; extern PropertyInfo qdev_prop_drive; extern PropertyInfo qdev_prop_netdev; extern PropertyInfo qdev_prop_vlan; extern PropertyInfo qdev_prop_pci_devfn; extern PropertyInfo qdev_prop_blocksize; extern PropertyInfo qdev_prop_pci_host_devaddr; #define DEFINE_PROP(_name, _state, _field, _prop, _type) { \ .name = (_name), \ .info = &(_prop), \ .offset = offsetof(_state, _field) \ + type_check(_type,typeof_field(_state, _field)), \ } #define DEFINE_PROP_DEFAULT(_name, _state, _field, _defval, _prop, _type) { \ .name = (_name), \ .info = &(_prop), \ .offset = offsetof(_state, _field) \ + type_check(_type,typeof_field(_state, _field)), \ .qtype = QTYPE_QINT, \ .defval = (_type)_defval, \ } #define DEFINE_PROP_BIT(_name, _state, _field, _bit, _defval) { \ .name = (_name), \ .info = &(qdev_prop_bit), \ .bitnr = (_bit), \ .offset = offsetof(_state, _field) \ + type_check(uint32_t,typeof_field(_state, _field)), \ .qtype = QTYPE_QBOOL, \ .defval = (bool)_defval, \ } #define DEFINE_PROP_UINT8(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_uint8, uint8_t) #define DEFINE_PROP_UINT16(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_uint16, uint16_t) #define DEFINE_PROP_UINT32(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_uint32, uint32_t) #define DEFINE_PROP_INT32(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_int32, int32_t) #define DEFINE_PROP_UINT64(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_uint64, uint64_t) #define DEFINE_PROP_HEX8(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_hex8, uint8_t) #define DEFINE_PROP_HEX32(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_hex32, uint32_t) #define DEFINE_PROP_HEX64(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_hex64, uint64_t) #define DEFINE_PROP_PCI_DEVFN(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_pci_devfn, int32_t) #define DEFINE_PROP_PTR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, void*) #define DEFINE_PROP_CHR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharDriverState*) #define DEFINE_PROP_STRING(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*) #define DEFINE_PROP_NETDEV(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_netdev, VLANClientState*) #define DEFINE_PROP_VLAN(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_vlan, VLANState*) #define DEFINE_PROP_DRIVE(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_drive, BlockDriverState *) #define DEFINE_PROP_MACADDR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) #define DEFINE_PROP_BIOS_CHS_TRANS(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_bios_chs_trans, int) #define DEFINE_PROP_BLOCKSIZE(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_blocksize, uint16_t) #define DEFINE_PROP_PCI_HOST_DEVADDR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_pci_host_devaddr, PCIHostDeviceAddress) #define DEFINE_PROP_END_OF_LIST() \ {} /* Set properties between creation and init. */ void *qdev_get_prop_ptr(DeviceState *dev, Property *prop); int qdev_prop_parse(DeviceState *dev, const char *name, const char *value); void qdev_prop_set_bit(DeviceState *dev, const char *name, bool value); void qdev_prop_set_uint8(DeviceState *dev, const char *name, uint8_t value); void qdev_prop_set_uint16(DeviceState *dev, const char *name, uint16_t value); void qdev_prop_set_uint32(DeviceState *dev, const char *name, uint32_t value); void qdev_prop_set_int32(DeviceState *dev, const char *name, int32_t value); void qdev_prop_set_uint64(DeviceState *dev, const char *name, uint64_t value); void qdev_prop_set_string(DeviceState *dev, const char *name, const char *value); void qdev_prop_set_chr(DeviceState *dev, const char *name, CharDriverState *value); void qdev_prop_set_netdev(DeviceState *dev, const char *name, VLANClientState *value); void qdev_prop_set_vlan(DeviceState *dev, const char *name, VLANState *value); int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState *value) QEMU_WARN_UNUSED_RESULT; void qdev_prop_set_drive_nofail(DeviceState *dev, const char *name, BlockDriverState *value); void qdev_prop_set_macaddr(DeviceState *dev, const char *name, uint8_t *value); void qdev_prop_set_enum(DeviceState *dev, const char *name, int value); /* FIXME: Remove opaque pointer properties. */ void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value); void qdev_prop_register_global_list(GlobalProperty *props); void qdev_prop_set_globals(DeviceState *dev); void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev, Property *prop, const char *value); char *qdev_get_fw_dev_path(DeviceState *dev); /** * @qdev_property_add_static - add a @Property to a device referencing a * field in a struct. */ void qdev_property_add_static(DeviceState *dev, Property *prop, Error **errp); /** * @qdev_machine_init * * Initialize platform devices before machine init. This is a hack until full * support for composition is added. */ void qdev_machine_init(void); /** * @device_reset * * Reset a single device (by calling the reset method). */ void device_reset(DeviceState *dev); const VMStateDescription *qdev_get_vmsd(DeviceState *dev); const char *qdev_fw_name(DeviceState *dev); Object *qdev_get_machine(void); /* FIXME: make this a link<> */ void qdev_set_parent_bus(DeviceState *dev, BusState *bus); extern int qdev_hotplug; char *qdev_get_dev_path(DeviceState *dev); #endif #n288'>288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 
// SPDX-License-Identifier: GPL-2.0-only
/*
 * mISDNinfineon.c
 *		Support for cards based on following Infineon ISDN chipsets
 *		- ISAC + HSCX
 *		- IPAC and IPAC-X
 *		- ISAC-SX + HSCX
 *
 * Supported cards:
 *		- Dialogic Diva 2.0
 *		- Dialogic Diva 2.0U
 *		- Dialogic Diva 2.01
 *		- Dialogic Diva 2.02
 *		- Sedlbauer Speedwin
 *		- HST Saphir3
 *		- Develo (former ELSA) Microlink PCI (Quickstep 1000)
 *		- Develo (former ELSA) Quickstep 3000
 *		- Berkom Scitel BRIX Quadro
 *		- Dr.Neuhaus (Sagem) Niccy
 *
 * Author       Karsten Keil <keil@isdn4linux.de>
 *
 * Copyright 2009  by Karsten Keil <keil@isdn4linux.de>
 */

#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/mISDNhw.h>
#include <linux/slab.h>
#include "ipac.h"

#define INFINEON_REV	"1.0"

static int inf_cnt;
static u32 debug;
static u32 irqloops = 4;

enum inf_types {
	INF_NONE,
	INF_DIVA20,
	INF_DIVA20U,
	INF_DIVA201,
	INF_DIVA202,
	INF_SPEEDWIN,
	INF_SAPHIR3,
	INF_QS1000,
	INF_QS3000,
	INF_NICCY,
	INF_SCT_1,
	INF_SCT_2,
	INF_SCT_3,
	INF_SCT_4,
	INF_GAZEL_R685,
	INF_GAZEL_R753
};

enum addr_mode {
	AM_NONE = 0,
	AM_IO,
	AM_MEMIO,
	AM_IND_IO,
};

struct inf_cinfo {
	enum inf_types	typ;
	const char	*full;
	const char	*name;
	enum addr_mode	cfg_mode;
	enum addr_mode	addr_mode;
	u8		cfg_bar;
	u8		addr_bar;
	void		*irqfunc;
};

struct _ioaddr {
	enum addr_mode	mode;
	union {
		void __iomem	*p;
		struct _ioport	io;
	} a;
};

struct _iohandle {
	enum addr_mode	mode;
	resource_size_t	size;
	resource_size_t	start;
	void __iomem	*p;
};

struct inf_hw {
	struct list_head	list;
	struct pci_dev		*pdev;
	const struct inf_cinfo	*ci;
	char			name[MISDN_MAX_IDLEN];
	u32			irq;
	u32			irqcnt;
	struct _iohandle	cfg;
	struct _iohandle	addr;
	struct _ioaddr		isac;
	struct _ioaddr		hscx;
	spinlock_t		lock;	/* HW access lock */
	struct ipac_hw		ipac;
	struct inf_hw		*sc[3];	/* slave cards */
};


#define PCI_SUBVENDOR_HST_SAPHIR3       0x52
#define PCI_SUBVENDOR_SEDLBAUER_PCI     0x53
#define PCI_SUB_ID_SEDLBAUER            0x01

static struct pci_device_id infineon_ids[] = {
	{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA20), INF_DIVA20 },
	{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA20_U), INF_DIVA20U },
	{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA201), INF_DIVA201 },
	{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA202), INF_DIVA202 },
	{ PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
	  PCI_SUBVENDOR_SEDLBAUER_PCI, PCI_SUB_ID_SEDLBAUER, 0, 0,
	  INF_SPEEDWIN },
	{ PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
	  PCI_SUBVENDOR_HST_SAPHIR3, PCI_SUB_ID_SEDLBAUER, 0, 0, INF_SAPHIR3 },
	{ PCI_VDEVICE(ELSA, PCI_DEVICE_ID_ELSA_MICROLINK), INF_QS1000 },
	{ PCI_VDEVICE(ELSA, PCI_DEVICE_ID_ELSA_QS3000), INF_QS3000 },
	{ PCI_VDEVICE(SATSAGEM, PCI_DEVICE_ID_SATSAGEM_NICCY), INF_NICCY },
	{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
	  PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO, 0, 0,
	  INF_SCT_1 },
	{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_R685), INF_GAZEL_R685 },
	{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_R753), INF_GAZEL_R753 },
	{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_DJINN_ITOO), INF_GAZEL_R753 },
	{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_OLITEC), INF_GAZEL_R753 },
	{ }
};
MODULE_DEVICE_TABLE(pci, infineon_ids);

/* PCI interface specific defines */
/* Diva 2.0/2.0U */
#define DIVA_HSCX_PORT		0x00
#define DIVA_HSCX_ALE		0x04
#define DIVA_ISAC_PORT		0x08
#define DIVA_ISAC_ALE		0x0C
#define DIVA_PCI_CTRL           0x10

/* DIVA_PCI_CTRL bits */
#define DIVA_IRQ_BIT		0x01
#define DIVA_RESET_BIT		0x08
#define DIVA_EEPROM_CLK		0x40
#define DIVA_LED_A		0x10
#define DIVA_LED_B		0x20
#define DIVA_IRQ_CLR		0x80

/* Diva 2.01/2.02 */
/* Siemens PITA */
#define PITA_ICR_REG		0x00
#define PITA_INT0_STATUS	0x02

#define PITA_MISC_REG		0x1c
#define PITA_PARA_SOFTRESET	0x01000000
#define PITA_SER_SOFTRESET	0x02000000
#define PITA_PARA_MPX_MODE	0x04000000
#define PITA_INT0_ENABLE	0x00020000

/* TIGER 100 Registers */
#define TIGER_RESET_ADDR	0x00
#define TIGER_EXTERN_RESET	0x01
#define TIGER_AUX_CTRL		0x02
#define TIGER_AUX_DATA		0x03
#define TIGER_AUX_IRQMASK	0x05
#define TIGER_AUX_STATUS	0x07

/* Tiger AUX BITs */
#define TIGER_IOMASK		0xdd	/* 1 and 5 are inputs */
#define TIGER_IRQ_BIT		0x02

#define TIGER_IPAC_ALE		0xC0
#define TIGER_IPAC_PORT		0xC8

/* ELSA (now Develo) PCI cards */
#define ELSA_IRQ_ADDR		0x4c
#define ELSA_IRQ_MASK		0x04
#define QS1000_IRQ_OFF		0x01
#define QS3000_IRQ_OFF		0x03
#define QS1000_IRQ_ON		0x41
#define QS3000_IRQ_ON		0x43

/* Dr Neuhaus/Sagem Niccy */
#define NICCY_ISAC_PORT		0x00
#define NICCY_HSCX_PORT		0x01
#define NICCY_ISAC_ALE		0x02
#define NICCY_HSCX_ALE		0x03

#define NICCY_IRQ_CTRL_REG	0x38
#define NICCY_IRQ_ENABLE	0x001f00
#define NICCY_IRQ_DISABLE	0xff0000
#define NICCY_IRQ_BIT		0x800000


/* Scitel PLX */
#define SCT_PLX_IRQ_ADDR	0x4c
#define SCT_PLX_RESET_ADDR	0x50
#define SCT_PLX_IRQ_ENABLE	0x41
#define SCT_PLX_RESET_BIT	0x04

/* Gazel */
#define	GAZEL_IPAC_DATA_PORT	0x04
/* Gazel PLX */
#define GAZEL_CNTRL		0x50
#define GAZEL_RESET		0x04
#define GAZEL_RESET_9050	0x40000000
#define GAZEL_INCSR		0x4C
#define GAZEL_ISAC_EN		0x08
#define GAZEL_INT_ISAC		0x20
#define GAZEL_HSCX_EN		0x01
#define GAZEL_INT_HSCX		0x04
#define GAZEL_PCI_EN		0x40
#define GAZEL_IPAC_EN		0x03


static LIST_HEAD(Cards);
static DEFINE_RWLOCK(card_lock); /* protect Cards */

static void
_set_debug(struct inf_hw *card)
{
	card->ipac.isac.dch.debug = debug;
	card->ipac.hscx[0].bch.debug = debug;
	card->ipac.hscx[1].bch.debug = debug;
}

static int
set_debug(const char *val, const struct kernel_param *kp)
{
	int ret;
	struct inf_hw *card;

	ret = param_set_uint(val, kp);
	if (!ret) {
		read_lock(&card_lock);
		list_for_each_entry(card, &Cards, list)
			_set_debug(card);
		read_unlock(&card_lock);
	}
	return ret;
}

MODULE_AUTHOR("Karsten Keil");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(INFINEON_REV);
module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(debug, "infineon debug mask");
module_param(irqloops, uint, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(irqloops, "infineon maximal irqloops (default 4)");

/* Interface functions */

IOFUNC_IO(ISAC, inf_hw, isac.a.io)
IOFUNC_IO(IPAC, inf_hw, hscx.a.io)
IOFUNC_IND(ISAC, inf_hw, isac.a.io)
IOFUNC_IND(IPAC, inf_hw, hscx.a.io)
IOFUNC_MEMIO(ISAC, inf_hw, u32, isac.a.p)
IOFUNC_MEMIO(IPAC, inf_hw, u32, hscx.a.p)

static irqreturn_t
diva_irq(int intno, void *dev_id)
{
	struct inf_hw *hw = dev_id;
	u8 val;

	spin_lock(&hw->lock);
	val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL);
	if (!(val & DIVA_IRQ_BIT)) { /* for us or shared ? */
		spin_unlock(&hw->lock);
		return IRQ_NONE; /* shared */
	}
	hw->irqcnt++;
	mISDNipac_irq(&hw->ipac, irqloops);
	spin_unlock(&hw->lock);
	return IRQ_HANDLED;
}

static irqreturn_t
diva20x_irq(int intno, void *dev_id)
{
	struct inf_hw *hw = dev_id;
	u8 val;

	spin_lock(&hw->lock);
	val = readb(hw->cfg.p);
	if (!(val & PITA_INT0_STATUS)) { /* for us or shared ? */
		spin_unlock(&hw->lock);
		return IRQ_NONE; /* shared */
	}
	hw->irqcnt++;
	mISDNipac_irq(&hw->ipac, irqloops);
	writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */
	spin_unlock(&hw->lock);
	return IRQ_HANDLED;
}

static irqreturn_t
tiger_irq(int intno, void *dev_id)
{
	struct inf_hw *hw = dev_id;
	u8 val;

	spin_lock(&hw->lock);
	val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS);
	if (val & TIGER_IRQ_BIT) { /* for us or shared ? */
		spin_unlock(&hw->lock);
		return IRQ_NONE; /* shared */
	}
	hw->irqcnt++;
	mISDNipac_irq(&hw->ipac, irqloops);
	spin_unlock(&hw->lock);
	return IRQ_HANDLED;
}

static irqreturn_t
elsa_irq(int intno, void *dev_id)
{
	struct inf_hw *hw = dev_id;
	u8 val;

	spin_lock(&hw->lock);
	val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR);
	if (!(val & ELSA_IRQ_MASK)) {
		spin_unlock(&hw->lock);
		return IRQ_NONE; /* shared */
	}
	hw->irqcnt++;
	mISDNipac_irq(&hw->ipac, irqloops);
	spin_unlock(&hw->lock);
	return IRQ_HANDLED;
}

static irqreturn_t
niccy_irq(int intno, void *dev_id)
{
	struct inf_hw *hw = dev_id;
	u32 val;

	spin_lock(&hw->lock);
	val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
	if (!(val & NICCY_IRQ_BIT)) { /* for us or shared ? */
		spin_unlock(&hw->lock);
		return IRQ_NONE; /* shared */
	}
	outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
	hw->irqcnt++;
	mISDNipac_irq(&hw->ipac, irqloops);
	spin_unlock(&hw->lock);
	return IRQ_HANDLED;
}

static irqreturn_t
gazel_irq(int intno, void *dev_id)
{
	struct inf_hw *hw = dev_id;
	irqreturn_t ret;

	spin_lock(&hw->lock);
	ret = mISDNipac_irq(&hw->ipac, irqloops);
	spin_unlock(&hw->lock);
	return ret;
}

static irqreturn_t
ipac_irq(int intno, void *dev_id)
{
	struct inf_hw *hw = dev_id;
	u8 val;

	spin_lock(&hw->lock);
	val = hw->ipac.read_reg(hw, IPAC_ISTA);
	if (!(val & 0x3f)) {
		spin_unlock(&hw->lock);
		return IRQ_NONE; /* shared */
	}
	hw->irqcnt++;
	mISDNipac_irq(&hw->ipac, irqloops);
	spin_unlock(&hw->lock);
	return IRQ_HANDLED;
}

static void
enable_hwirq(struct inf_hw *hw)
{
	u16 w;
	u32 val;

	switch (hw->ci->typ) {
	case INF_DIVA201:
	case INF_DIVA202:
		writel(PITA_INT0_ENABLE, hw->cfg.p);
		break;
	case INF_SPEEDWIN:
	case INF_SAPHIR3:
		outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
		break;
	case INF_QS1000:
		outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
		break;
	case INF_QS3000:
		outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
		break;
	case INF_NICCY:
		val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
		val |= NICCY_IRQ_ENABLE;
		outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
		break;
	case INF_SCT_1:
		w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
		w |= SCT_PLX_IRQ_ENABLE;
		outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
		break;
	case INF_GAZEL_R685:
		outb(GAZEL_ISAC_EN + GAZEL_HSCX_EN + GAZEL_PCI_EN,
		     (u32)hw->cfg.start + GAZEL_INCSR);
		break;
	case INF_GAZEL_R753:
		outb(GAZEL_IPAC_EN + GAZEL_PCI_EN,
		     (u32)hw->cfg.start + GAZEL_INCSR);
		break;
	default:
		break;
	}
}

static void
disable_hwirq(struct inf_hw *hw)
{
	u16 w;
	u32 val;

	switch (hw->ci->typ) {
	case INF_DIVA201:
	case INF_DIVA202:
		writel(0, hw->cfg.p);
		break;
	case INF_SPEEDWIN:
	case INF_SAPHIR3:
		outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
		break;
	case INF_QS1000:
		outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
		break;
	case INF_QS3000:
		outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
		break;
	case INF_NICCY:
		val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
		val &= NICCY_IRQ_DISABLE;
		outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
		break;
	case INF_SCT_1:
		w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
		w &= (~SCT_PLX_IRQ_ENABLE);
		outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
		break;
	case INF_GAZEL_R685:
	case INF_GAZEL_R753:
		outb(0, (u32)hw->cfg.start + GAZEL_INCSR);
		break;
	default:
		break;
	}
}

static void
ipac_chip_reset(struct inf_hw *hw)
{
	hw->ipac.write_reg(hw, IPAC_POTA2, 0x20);
	mdelay(5);
	hw->ipac.write_reg(hw, IPAC_POTA2, 0x00);
	mdelay(5);
	hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf);
	hw->ipac.write_reg(hw, IPAC_MASK, 0xc0);
}

static void
reset_inf(struct inf_hw *hw)
{
	u16 w;
	u32 val;

	if (debug & DEBUG_HW)
		pr_notice("%s: resetting card\n", hw->name);
	switch (hw->ci->typ) {
	case INF_DIVA20:
	case INF_DIVA20U:
		outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL);
		mdelay(10);
		outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL);
		mdelay(10);
		/* Workaround PCI9060 */
		outb(9, (u32)hw->cfg.start + 0x69);
		outb(DIVA_RESET_BIT | DIVA_LED_A,
		     (u32)hw->cfg.start + DIVA_PCI_CTRL);
		break;
	case INF_DIVA201:
		writel(PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE,
		       hw->cfg.p + PITA_MISC_REG);
		mdelay(1);
		writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG);
		mdelay(10);
		break;
	case INF_DIVA202:
		writel(PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE,
		       hw->cfg.p + PITA_MISC_REG);
		mdelay(1);
		writel(PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET,
		       hw->cfg.p + PITA_MISC_REG);
		mdelay(10);
		break;
	case INF_SPEEDWIN:
	case INF_SAPHIR3:
		ipac_chip_reset(hw);
		hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
		hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
		hw->ipac.write_reg(hw, IPAC_PCFG, 0x12);
		break;
	case INF_QS1000:
	case INF_QS3000:
		ipac_chip_reset(hw);
		hw->ipac.write_reg(hw, IPAC_ACFG, 0x00);
		hw->ipac.write_reg(hw, IPAC_AOE, 0x3c);
		hw->ipac.write_reg(hw, IPAC_ATX, 0xff);
		break;
	case INF_NICCY:
		break;
	case INF_SCT_1:
		w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
		w &= (~SCT_PLX_RESET_BIT);
		outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
		mdelay(10);
		w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
		w |= SCT_PLX_RESET_BIT;
		outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
		mdelay(10);
		break;
	case INF_GAZEL_R685:
		val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
		val |= (GAZEL_RESET_9050 + GAZEL_RESET);
		outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
		val &= ~(GAZEL_RESET_9050 + GAZEL_RESET);
		mdelay(4);
		outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
		mdelay(10);
		hw->ipac.isac.adf2 = 0x87;
		hw->ipac.hscx[0].slot = 0x1f;
		hw->ipac.hscx[1].slot = 0x23;
		break;
	case INF_GAZEL_R753:
		val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
		val |= (GAZEL_RESET_9050 + GAZEL_RESET);
		outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
		val &= ~(GAZEL_RESET_9050 + GAZEL_RESET);
		mdelay(4);
		outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
		mdelay(10);
		ipac_chip_reset(hw);
		hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
		hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
		hw->ipac.conf = 0x01; /* IOM off */
		break;
	default:
		return;
	}
	enable_hwirq(hw);
}

static int
inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg)
{
	int ret = 0;

	switch (cmd) {
	case HW_RESET_REQ:
		reset_inf(hw);
		break;
	default:
		pr_info("%s: %s unknown command %x %lx\n",
			hw->name, __func__, cmd, arg);
		ret = -EINVAL;
		break;
	}
	return ret;
}

static int
init_irq(struct inf_hw *hw)
{
	int	ret, cnt = 3;
	u_long	flags;

	if (!hw->ci->irqfunc)
		return -EINVAL;
	ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw);
	if (ret) {
		pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq);
		return ret;
	}
	while (cnt--) {
		spin_lock_irqsave(&hw->lock, flags);
		reset_inf(hw);
		ret = hw->ipac.init(&hw->ipac);
		if (ret) {
			spin_unlock_irqrestore(&hw->lock, flags);
			pr_info("%s: ISAC init failed with %d\n",
				hw->name, ret);
			break;
		}
		spin_unlock_irqrestore(&hw->lock, flags);
		msleep_interruptible(10);
		if (debug & DEBUG_HW)
			pr_notice("%s: IRQ %d count %d\n", hw->name,
				  hw->irq, hw->irqcnt);
		if (!hw->irqcnt) {
			pr_info("%s: IRQ(%d) got no requests during init %d\n",
				hw->name, hw->irq, 3 - cnt);
		} else
			return 0;
	}
	free_irq(hw->irq, hw);
	return -EIO;
}

static void
release_io(struct inf_hw *hw)
{
	if (hw->cfg.mode) {
		if (hw->cfg.p) {
			release_mem_region(hw->cfg.start, hw->cfg.size);
			iounmap(hw->cfg.p);
		} else
			release_region(hw->cfg.start, hw->cfg.size);
		hw->cfg.mode = AM_NONE;
	}
	if (hw->addr.mode) {
		if (hw->addr.p) {
			release_mem_region(hw->addr.start, hw->addr.size);
			iounmap(hw->addr.p);
		} else
			release_region(hw->addr.start, hw->addr.size);
		hw->addr.mode = AM_NONE;
	}
}

static int
setup_io(struct inf_hw *hw)
{
	int err = 0;

	if (hw->ci->cfg_mode) {
		hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar);
		hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar);
		if (hw->ci->cfg_mode == AM_MEMIO) {
			if (!request_mem_region(hw->cfg.start, hw->cfg.size,
						hw->name))
				err = -EBUSY;
		} else {
			if (!request_region(hw->cfg.start, hw->cfg.size,
					    hw->name))
				err = -EBUSY;
		}
		if (err) {
			pr_info("mISDN: %s config port %lx (%lu bytes)"
				"already in use\n", hw->name,
				(ulong)hw->cfg.start, (ulong)hw->cfg.size);
			return err;
		}
		if (hw->ci->cfg_mode == AM_MEMIO)
			hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size);
		hw->cfg.mode = hw->ci->cfg_mode;
		if (debug & DEBUG_HW)
			pr_notice("%s: IO cfg %lx (%lu bytes) mode%d\n",
				  hw->name, (ulong)hw->cfg.start,
				  (ulong)hw->cfg.size, hw->ci->cfg_mode);

	}
	if (hw->ci->addr_mode) {
		hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar);
		hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar);
		if (hw->ci->addr_mode == AM_MEMIO) {
			if (!request_mem_region(hw->addr.start, hw->addr.size,
						hw->name))
				err = -EBUSY;
		} else {
			if (!request_region(hw->addr.start, hw->addr.size,
					    hw->name))
				err = -EBUSY;
		}
		if (err) {
			pr_info("mISDN: %s address port %lx (%lu bytes)"
				"already in use\n", hw->name,
				(ulong)hw->addr.start, (ulong)hw->addr.size);
			return err;
		}
		if (hw->ci->addr_mode == AM_MEMIO) {
			hw->addr.p = ioremap(hw->addr.start, hw->addr.size);
			if (unlikely(!hw->addr.p))
				return -ENOMEM;
		}
		hw->addr.mode = hw->ci->addr_mode;
		if (debug & DEBUG_HW)
			pr_notice("%s: IO addr %lx (%lu bytes) mode%d\n",
				  hw->name, (ulong)hw->addr.start,
				  (ulong)hw->addr.size, hw->ci->addr_mode);

	}

	switch (hw->ci->typ) {
	case INF_DIVA20:
	case INF_DIVA20U:
		hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
		hw->isac.mode = hw->cfg.mode;
		hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE;
		hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT;
		hw->hscx.mode = hw->cfg.mode;
		hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE;
		hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT;
		break;
	case INF_DIVA201:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.mode = hw->addr.mode;
		hw->isac.a.p = hw->addr.p;
		hw->hscx.mode = hw->addr.mode;
		hw->hscx.a.p = hw->addr.p;
		break;
	case INF_DIVA202:
		hw->ipac.type = IPAC_TYPE_IPACX;
		hw->isac.mode = hw->addr.mode;
		hw->isac.a.p = hw->addr.p;
		hw->hscx.mode = hw->addr.mode;
		hw->hscx.a.p = hw->addr.p;
		break;
	case INF_SPEEDWIN:
	case INF_SAPHIR3:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.mode = hw->cfg.mode;
		hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
		hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
		hw->hscx.mode = hw->cfg.mode;
		hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
		hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
		outb(0xff, (ulong)hw->cfg.start);
		mdelay(1);
		outb(0x00, (ulong)hw->cfg.start);
		mdelay(1);
		outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL);
		break;
	case INF_QS1000:
	case INF_QS3000:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.a.io.ale = (u32)hw->addr.start;
		hw->isac.a.io.port = (u32)hw->addr.start + 1;
		hw->isac.mode = hw->addr.mode;
		hw->hscx.a.io.ale = (u32)hw->addr.start;
		hw->hscx.a.io.port = (u32)hw->addr.start + 1;
		hw->hscx.mode = hw->addr.mode;
		break;
	case INF_NICCY:
		hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
		hw->isac.mode = hw->addr.mode;
		hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE;
		hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT;
		hw->hscx.mode = hw->addr.mode;
		hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE;
		hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT;
		break;
	case INF_SCT_1:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.a.io.ale = (u32)hw->addr.start;
		hw->isac.a.io.port = hw->isac.a.io.ale + 4;
		hw->isac.mode = hw->addr.mode;
		hw->hscx.a.io.ale = hw->isac.a.io.ale;
		hw->hscx.a.io.port = hw->isac.a.io.port;
		hw->hscx.mode = hw->addr.mode;
		break;
	case INF_SCT_2:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.a.io.ale = (u32)hw->addr.start + 0x08;
		hw->isac.a.io.port = hw->isac.a.io.ale + 4;
		hw->isac.mode = hw->addr.mode;
		hw->hscx.a.io.ale = hw->isac.a.io.ale;
		hw->hscx.a.io.port = hw->isac.a.io.port;
		hw->hscx.mode = hw->addr.mode;
		break;
	case INF_SCT_3:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.a.io.ale = (u32)hw->addr.start + 0x10;
		hw->isac.a.io.port = hw->isac.a.io.ale + 4;
		hw->isac.mode = hw->addr.mode;
		hw->hscx.a.io.ale = hw->isac.a.io.ale;
		hw->hscx.a.io.port = hw->isac.a.io.port;
		hw->hscx.mode = hw->addr.mode;
		break;
	case INF_SCT_4:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.a.io.ale = (u32)hw->addr.start + 0x20;
		hw->isac.a.io.port = hw->isac.a.io.ale + 4;
		hw->isac.mode = hw->addr.mode;
		hw->hscx.a.io.ale = hw->isac.a.io.ale;
		hw->hscx.a.io.port = hw->isac.a.io.port;
		hw->hscx.mode = hw->addr.mode;
		break;
	case INF_GAZEL_R685:
		hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
		hw->ipac.isac.off = 0x80;
		hw->isac.mode = hw->addr.mode;
		hw->isac.a.io.port = (u32)hw->addr.start;
		hw->hscx.mode = hw->addr.mode;
		hw->hscx.a.io.port = hw->isac.a.io.port;
		break;
	case INF_GAZEL_R753:
		hw->ipac.type = IPAC_TYPE_IPAC;
		hw->ipac.isac.off = 0x80;
		hw->isac.mode = hw->addr.mode;
		hw->isac.a.io.ale = (u32)hw->addr.start;
		hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT;
		hw->hscx.mode = hw->addr.mode;
		hw->hscx.a.io.ale = hw->isac.a.io.ale;
		hw->hscx.a.io.port = hw->isac.a.io.port;
		break;
	default:
		return -EINVAL;
	}
	switch (hw->isac.mode) {
	case AM_MEMIO:
		ASSIGN_FUNC_IPAC(MIO, hw->ipac);
		break;
	case AM_IND_IO:
		ASSIGN_FUNC_IPAC(IND, hw->ipac);
		break;
	case AM_IO:
		ASSIGN_FUNC_IPAC(IO, hw->ipac);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static void
release_card(struct inf_hw *card) {
	ulong	flags;
	int	i;

	spin_lock_irqsave(&card->lock, flags);
	disable_hwirq(card);
	spin_unlock_irqrestore(&card->lock, flags);
	card->ipac.isac.release(&card->ipac.isac);
	free_irq(card->irq, card);
	mISDN_unregister_device(&card->ipac.isac.dch.dev);
	release_io(card);
	write_lock_irqsave(&card_lock, flags);
	list_del(&card->list);
	write_unlock_irqrestore(&card_lock, flags);
	switch (card->ci->typ) {
	case INF_SCT_2:
	case INF_SCT_3:
	case INF_SCT_4:
		break;
	case INF_SCT_1:
		for (i = 0; i < 3; i++) {
			if (card->sc[i])
				release_card(card->sc[i]);
			card->sc[i] = NULL;
		}
		/* fall through */
	default:
		pci_disable_device(card->pdev);
		pci_set_drvdata(card->pdev, NULL);
		break;
	}
	kfree(card);
	inf_cnt--;
}

static int
setup_instance(struct inf_hw *card)
{
	int err;
	ulong flags;

	snprintf(card->name, MISDN_MAX_IDLEN - 1, "%s.%d", card->ci->name,
		 inf_cnt + 1);
	write_lock_irqsave(&card_lock, flags);
	list_add_tail(&card->list, &Cards);
	write_unlock_irqrestore(&card_lock, flags);

	_set_debug(card);
	card->ipac.isac.name = card->name;
	card->ipac.name = card->name;
	card->ipac.owner = THIS_MODULE;
	spin_lock_init(&card->lock);
	card->ipac.isac.hwlock = &card->lock;
	card->ipac.hwlock = &card->lock;
	card->ipac.ctrl = (void *)&inf_ctrl;

	err = setup_io(card);
	if (err)
		goto error_setup;

	card->ipac.isac.dch.dev.Bprotocols =
		mISDNipac_init(&card->ipac, card);

	if (card->ipac.isac.dch.dev.Bprotocols == 0)
		goto error_setup;

	err = mISDN_register_device(&card->ipac.isac.dch.dev,
				    &card->pdev->dev, card->name);
	if (err)
		goto error;

	err = init_irq(card);
	if (!err)  {
		inf_cnt++;
		pr_notice("Infineon %d cards installed\n", inf_cnt);
		return 0;
	}
	mISDN_unregister_device(&card->ipac.isac.dch.dev);
error:
	card->ipac.release(&card->ipac);
error_setup:
	release_io(card);
	write_lock_irqsave(&card_lock, flags);
	list_del(&card->list);
	write_unlock_irqrestore(&card_lock, flags);
	return err;
}

static const struct inf_cinfo inf_card_info[] = {
	{
		INF_DIVA20,
		"Dialogic Diva 2.0",
		"diva20",
		AM_IND_IO, AM_NONE, 2, 0,
		&diva_irq
	},
	{
		INF_DIVA20U,
		"Dialogic Diva 2.0U",
		"diva20U",
		AM_IND_IO, AM_NONE, 2, 0,
		&diva_irq
	},
	{
		INF_DIVA201,
		"Dialogic Diva 2.01",
		"diva201",
		AM_MEMIO, AM_MEMIO, 0, 1,
		&diva20x_irq
	},
	{
		INF_DIVA202,
		"Dialogic Diva 2.02",
		"diva202",
		AM_MEMIO, AM_MEMIO, 0, 1,
		&diva20x_irq
	},
	{
		INF_SPEEDWIN,
		"Sedlbauer SpeedWin PCI",
		"speedwin",
		AM_IND_IO, AM_NONE, 0, 0,
		&tiger_irq
	},
	{
		INF_SAPHIR3,
		"HST Saphir 3",
		"saphir",
		AM_IND_IO, AM_NONE, 0, 0,
		&tiger_irq
	},
	{
		INF_QS1000,
		"Develo Microlink PCI",
		"qs1000",
		AM_IO, AM_IND_IO, 1, 3,
		&elsa_irq
	},
	{
		INF_QS3000,
		"Develo QuickStep 3000",
		"qs3000",
		AM_IO, AM_IND_IO, 1, 3,
		&elsa_irq
	},
	{
		INF_NICCY,
		"Sagem NICCY",
		"niccy",
		AM_IO, AM_IND_IO, 0, 1,
		&niccy_irq
	},
	{
		INF_SCT_1,
		"SciTel Quadro",
		"p1_scitel",
		AM_IO, AM_IND_IO, 1, 5,
		&ipac_irq
	},
	{
		INF_SCT_2,
		"SciTel Quadro",
		"p2_scitel",
		AM_NONE, AM_IND_IO, 0, 4,
		&ipac_irq
	},
	{
		INF_SCT_3,
		"SciTel Quadro",
		"p3_scitel",
		AM_NONE, AM_IND_IO, 0, 3,
		&ipac_irq
	},
	{
		INF_SCT_4,
		"SciTel Quadro",
		"p4_scitel",
		AM_NONE, AM_IND_IO, 0, 2,
		&ipac_irq
	},
	{
		INF_GAZEL_R685,
		"Gazel R685",
		"gazel685",
		AM_IO, AM_IO, 1, 2,
		&gazel_irq
	},
	{
		INF_GAZEL_R753,
		"Gazel R753",
		"gazel753",
		AM_IO, AM_IND_IO, 1, 2,
		&ipac_irq
	},
	{
		INF_NONE,
	}
};

static const struct inf_cinfo *
get_card_info(enum inf_types typ)
{
	const struct inf_cinfo *ci = inf_card_info;

	while (ci->typ != INF_NONE) {
		if (ci->typ == typ)
			return ci;
		ci++;
	}
	return NULL;
}

static int
inf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	int err = -ENOMEM;
	struct inf_hw *card;

	card = kzalloc(sizeof(struct inf_hw), GFP_KERNEL);
	if (!card) {
		pr_info("No memory for Infineon ISDN card\n");
		return err;
	}
	card->pdev = pdev;
	err = pci_enable_device(pdev);
	if (err) {
		kfree(card);
		return err;
	}
	card->ci = get_card_info(ent->driver_data);
	if (!card->ci) {
		pr_info("mISDN: do not have information about adapter at %s\n",
			pci_name(pdev));
		kfree(card);
		pci_disable_device(pdev);
		return -EINVAL;
	} else
		pr_notice("mISDN: found adapter %s at %s\n",
			  card->ci->full, pci_name(pdev));

	card->irq = pdev->irq;
	pci_set_drvdata(pdev, card);
	err = setup_instance(card);
	if (err) {
		pci_disable_device(pdev);
		kfree(card);
		pci_set_drvdata(pdev, NULL);
	} else if (ent->driver_data == INF_SCT_1) {
		int i;
		struct inf_hw *sc;

		for (i = 1; i < 4; i++) {
			sc = kzalloc(sizeof(struct inf_hw), GFP_KERNEL);
			if (!sc) {
				release_card(card);
				pci_disable_device(pdev);
				return -ENOMEM;
			}
			sc->irq = card->irq;
			sc->pdev = card->pdev;
			sc->ci = card->ci + i;
			err = setup_instance(sc);
			if (err) {
				pci_disable_device(pdev);
				kfree(sc);
				release_card(card);
				break;
			} else
				card->sc[i - 1] = sc;
		}
	}
	return err;
}

static void
inf_remove(struct pci_dev *pdev)
{
	struct inf_hw	*card = pci_get_drvdata(pdev);

	if (card)
		release_card(card);
	else
		pr_debug("%s: drvdata already removed\n", __func__);
}

static struct pci_driver infineon_driver = {
	.name = "ISDN Infineon pci",
	.probe = inf_probe,
	.remove = inf_remove,
	.id_table = infineon_ids,
};

static int __init
infineon_init(void)
{
	int err;

	pr_notice("Infineon ISDN Driver Rev. %s\n", INFINEON_REV);
	err = pci_register_driver(&infineon_driver);
	return err;
}

static void __exit
infineon_cleanup(void)
{
	pci_unregister_driver(&infineon_driver);
}

module_init(infineon_init);
module_exit(infineon_cleanup);
generated by cgit (git 2.34.1) at 2025-02-26 15:54:26 +0000