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#ifndef A3000_H
#define A3000_H

/* $Id: a3000.h,v 1.4 1997/01/19 23:07:10 davem Exp $
 *
 * Header file for the Amiga 3000 built-in SCSI controller for Linux
 *
 * Written and (C) 1993, Hamish Macdonald, see a3000.c for more info
 *
 */

#include <linux/types.h>

int a3000_detect(struct scsi_host_template *);
int a3000_release(struct Scsi_Host *);

#ifndef CMD_PER_LUN
#define CMD_PER_LUN 2
#endif

#ifndef CAN_QUEUE
#define CAN_QUEUE 16
#endif

/*
 * if the transfer address ANDed with this results in a non-zero
 * result, then we can't use DMA.
 */
#define A3000_XFER_MASK  (0x00000003)

typedef struct {
             unsigned char      pad1[2];
    volatile unsigned short     DAWR;
    volatile unsigned int       WTC;
             unsigned char      pad2[2];
    volatile unsigned short     CNTR;
    volatile unsigned long      ACR;
             unsigned char      pad3[2];
    volatile unsigned short     ST_DMA;
             unsigned char      pad4[2];
    volatile unsigned short     FLUSH;
             unsigned char      pad5[2];
    volatile unsigned short     CINT;
             unsigned char      pad6[2];
    volatile unsigned short     ISTR;
	     unsigned char      pad7[30];
    volatile unsigned short     SP_DMA;
             unsigned char      pad8;
    volatile unsigned char      SASR;
             unsigned char      pad9;
    volatile unsigned char      SCMD;
} a3000_scsiregs;

#define DAWR_A3000		(3)

/* CNTR bits. */
#define CNTR_TCEN		(1<<5)
#define CNTR_PREST		(1<<4)
#define CNTR_PDMD		(1<<3)
#define CNTR_INTEN		(1<<2)
#define CNTR_DDIR		(1<<1)
#define CNTR_IO_DX		(1<<0)

/* ISTR bits. */
#define ISTR_INTX		(1<<8)
#define ISTR_INT_F		(1<<7)
#define ISTR_INTS		(1<<6)
#define ISTR_E_INT		(1<<5)
#define ISTR_INT_P		(1<<4)
#define ISTR_UE_INT		(1<<3)
#define ISTR_OE_INT		(1<<2)
#define ISTR_FF_FLG		(1<<1)
#define ISTR_FE_FLG		(1<<0)

#endif /* A3000_H */
* * * These are the low level assembler for performing cache and TLB * functions on the fa526. */ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> #include <asm/hwcap.h> #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> #include <asm/page.h> #include <asm/ptrace.h> #include <asm/system.h> #include "proc-macros.S" #define CACHE_DLINESIZE 16 .text /* * cpu_fa526_proc_init() */ ENTRY(cpu_fa526_proc_init) mov pc, lr /* * cpu_fa526_proc_fin() */ ENTRY(cpu_fa526_proc_fin) mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. mcr p15, 0, r0, c1, c0, 0 @ disable caches nop nop mov pc, lr /* * cpu_fa526_reset(loc) * * Perform a soft reset of the system. Put the CPU into the * same state as it would be if it had been reset, and branch * to what would be the reset vector. * * loc: location to jump to for soft reset */ .align 4 ENTRY(cpu_fa526_reset) /* TODO: Use CP8 if possible... */ mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches mcr p15, 0, ip, c7, c10, 4 @ drain WB #ifdef CONFIG_MMU mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs #endif mrc p15, 0, ip, c1, c0, 0 @ ctrl register bic ip, ip, #0x000f @ ............wcam bic ip, ip, #0x1100 @ ...i...s........ bic ip, ip, #0x0800 @ BTB off mcr p15, 0, ip, c1, c0, 0 @ ctrl register nop nop mov pc, r0 /* * cpu_fa526_do_idle() */ .align 4 ENTRY(cpu_fa526_do_idle) mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt mov pc, lr ENTRY(cpu_fa526_dcache_clean_area) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE subs r1, r1, #CACHE_DLINESIZE bhi 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr /* =============================== PageTable ============================== */ /* * cpu_fa526_switch_mm(pgd) * * Set the translation base pointer to be as described by pgd. * * pgd: new page tables */ .align 4 ENTRY(cpu_fa526_switch_mm) #ifdef CONFIG_MMU mov ip, #0 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache #else mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache #endif mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed mcr p15, 0, ip, c7, c10, 4 @ data write barrier mcr p15, 0, ip, c7, c5, 4 @ prefetch flush mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB #endif mov pc, lr /* * cpu_fa526_set_pte_ext(ptep, pte, ext) * * Set a PTE and flush it out */ .align 4 ENTRY(cpu_fa526_set_pte_ext) #ifdef CONFIG_MMU armv3_set_pte_ext mov r0, r0 mcr p15, 0, r0, c7, c10, 1 @ clean D entry mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain WB #endif mov pc, lr __CPUINIT .type __fa526_setup, #function __fa526_setup: /* On return of this routine, r0 must carry correct flags for CFG register */ mov r0, #0 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM mov r0, #1 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR mov r0, #0 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c5, 4 @ prefetch flush mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client mcr p15, 0, r0, c3, c0 @ load domain access register mrc p15, 0, r0, c1, c0 @ get control register v4 ldr r5, fa526_cr1_clear bic r0, r0, r5 ldr r5, fa526_cr1_set orr r0, r0, r5 mov pc, lr .size __fa526_setup, . - __fa526_setup /* * .RVI ZFRS BLDP WCAM * ..11 1001 .111 1101 * */ .type fa526_cr1_clear, #object .type fa526_cr1_set, #object fa526_cr1_clear: .word 0x3f3f fa526_cr1_set: .word 0x397D __INITDATA @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort .section ".rodata" string cpu_arch_name, "armv4" string cpu_elf_name, "v4" string cpu_fa526_name, "FA526" .align .section ".proc.info.init", #alloc, #execinstr .type __fa526_proc_info,#object __fa526_proc_info: .long 0x66015261 .long 0xff01fff1 .long PMD_TYPE_SECT | \ PMD_SECT_BUFFERABLE | \ PMD_SECT_CACHEABLE | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ .long PMD_TYPE_SECT | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ b __fa526_setup .long cpu_arch_name .long cpu_elf_name .long HWCAP_SWP | HWCAP_HALF .long cpu_fa526_name .long fa526_processor_functions .long fa_tlb_fns .long fa_user_fns .long fa_cache_fns .size __fa526_proc_info, . - __fa526_proc_info