diff options
| author | Zhang, Chao B <chao.b.zhang@intel.com> | 2017-12-12 15:38:20 +0800 |
|---|---|---|
| committer | Zhang, Chao B <chao.b.zhang@intel.com> | 2018-03-22 10:30:58 +0800 |
| commit | 2f8435946aa2c0e35a419808f052a3114b914739 (patch) | |
| tree | 089a86b62989843ed299c5feb044d03632ef0463 | |
| parent | 3302acc9f8307a88a4d11788bac7869ca978786d (diff) | |
| download | edk2-2f8435946aa2c0e35a419808f052a3114b914739.tar.gz | |
SecurityPkg:Tcg2Smm: Update Interrupt resource name
Update TPM interrupt resource descriptor name for better compatibility to
old ASL compiler.
Cc: Long Qin <qin.long@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Long Qin <qin.long@intel.com>
(cherry picked from commit 73d777329f84b5f4acdbc4369b56c0670e873cff)
(cherry picked from commit 1eff644477b0a2bf46cfde4801aa7bc16a11043e)
| -rw-r--r-- | SecurityPkg/Tcg/Tcg2Smm/Tpm.asl | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl index 30b39a2a31..c943895e92 100644 --- a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl +++ b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl @@ -97,7 +97,7 @@ DefinitionBlock ( Name(RESO, ResourceTemplate () {
Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS)
- Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12}
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , INTR) {12}
})
//
@@ -120,16 +120,16 @@ DefinitionBlock ( // Use the field name to identify the offsets in the argument
// buffer and RESO buffer.
//
- CreateDWordField(Arg0, ^IRQ._INT, IRQ0)
- CreateDWordField(RESO, ^IRQ._INT, LIRQ)
+ CreateDWordField(Arg0, ^INTR._INT, IRQ0)
+ CreateDWordField(RESO, ^INTR._INT, LIRQ)
Store(IRQ0, LIRQ)
- CreateBitField(Arg0, ^IRQ._HE, ITRG)
- CreateBitField(RESO, ^IRQ._HE, LTRG)
+ CreateBitField(Arg0, ^INTR._HE, ITRG)
+ CreateBitField(RESO, ^INTR._HE, LTRG)
Store(ITRG, LTRG)
- CreateBitField(Arg0, ^IRQ._LL, ILVL)
- CreateBitField(RESO, ^IRQ._LL, LLVL)
+ CreateBitField(Arg0, ^INTR._LL, ILVL)
+ CreateBitField(RESO, ^INTR._LL, LLVL)
Store(ILVL, LLVL)
//
|